How to use PSRAM on ESP32-S3 NON VOLATILE to CPU reset in IDF

[MichaelS]

Hi
I have a project using ESP32-S3 modules and IDF.
I want to use the PSRAM as memory which is non volatile across a CPU reset. I understand it is NOT non volatile over a power loss.
I want to be able to store data records in a FIFO type structure.
What is the best strategy for doing this?

A VFS RAM disk with non volatile across a reset would also be a good solution, but does not seem the exist?

I tried enabling PSRAM and using heap_caps_malloc(..., MALLOC_CAP_SPIRAM) and found that while I could access the RAM fine, I realized the memory contents would be lost after a reset by the allocation and creation of a variables with a custom allocator. Is there any way of avoiding this and also ensuring the allocation is repeatable across a reset?

I also found when the PSRAM was enabled (in Menu config) but not even used (no calls to heap_caps_malloc(..., MALLOC_CAP_SPIRAM)), my application went a bit weird. OTA updates using HTTPS slowed down and eventually failed. My OTTA HTTPS code was taken from IDF example "advanced_https_ota". Is there something I could have done wrong or could set to fix this? I can reproduce the problem just by enabling PSRAM (in menu-config) and fix it by disabling it again.

So I thought I would have to write my own interface where I can control the memory addressing and ensure no initialization or clearing happens on CPU rest.
I looked at the data sheet of the ESP32­S3­WROOM­1 module to find out what GPIO are used for the PSRAM SPI bus and am now very confused.
Section 5 Module Schematics does not show any PSRAM chip? Is it built into the ESP32 SOC?
Also for the SPI Flash it shows standard SPI when I thought it would be octal-SPI or quad-SPI? Is this not the main program Flash, and is it also built into the ESP32 SOC