Stream 36bit serial signal into the DMA…

[stefan]

I want to receive a rather odd serial data stream with the ESP32 DMA.

The signal for a YAC512 DAC [a 90s "floating point DAC" taking the input from an YMF262/OPL3 soundchip].
Basically a frame consists of 36bit -> 2x 16bit + 2bit padding each.
Data used by the DAC is 3bit padding (not used by YAC512, but valid data as far as I found out) + 10bit mantissa + 3bit exponent.

SCLK ist around 1.8MHz.
36bit frames come in at around 50kHz.

There are 2 pins that act as sort of a I2S WordClock.
Those go HIGH after the first 8bit have been clocked in and LOW when the second 8bit are in.
That's when the internal latch of the YAC512 would activate.

What I want to do:
- Get the complete data stream (minus the padding)
- Multiply mantissa and exponent and arrange bits to get a PCM stream
- Send out the converted data via I2S.
- Best case: I am able to capture both serial streams [not sure yet if the ESP32 I2S can do > 2ch] (the OPL3 has 4ch output and thus 2 serial signals, requiring 2x YAC512)
- No further functionality is needed. WiFi off, whatever is best.

I was thinking about possible approaches:
#1 Attach a shift register to each of the two signal lines, run a pin-change-detection loop on the 2nd core (WDT and INT disabled), pull the shift register latches, input the 16 bit via the I2S camera mode in parallel, process, output. Running out of pins for the output tho…
#2 Same as #1 but with only one serial input, thus freeing pins for the output.
#3 Tricking the I2S peripheral into serially capturing the data, skipping the padding and spitting it into the DMA for processing.
#4 Using the SPI peripheral in slave mode, setting length and trans_length in spi_slave_transaction_t to 324 bit (9 complete frames back-to-back) and then process that "en-block", using one of the WordClock signals to sync the start. Not sure what I end up with on the data side – 40 bytes of data plus 1 byte with 4 bit data + 4 bit padding?
#5 Run a raw, brute force GPIO-scan loop on the 5 input signals with core_1 > push that byte into the DMA > core_0 grabs the stream and re-aranges 32 of those bytes into a full frame, post-processes hands over to the I2S DMA for output.

So basically I am not sure which of those approaches are even possible – obviously using zero extra components is always cooler – but this being a DAC, it has to be a constant cycle of input > processing > output with a minimum of glitching.

Attached is a capture of the raw signal with timing annotations.