Start a SPI DMA transmission by GPIO trigger ? - ESP32-S3 Forum

[ok-home]

I don't really understand the question
in the code you are running the pwm over gpio5 (DRDY)
do a single run not a constant generation

Code: Select all

/**
 * @brief MCPWM timer commands, specify the way to start or stop the timer
 */
typedef enum {
    MCPWM_TIMER_STOP_EMPTY,       /*!< MCPWM timer stops when next count reaches zero */
    MCPWM_TIMER_STOP_FULL,        /*!< MCPWM timer stops when next count reaches peak */
    MCPWM_TIMER_START_NO_STOP,    /*!< MCPWM timer starts couting, and don't stop until received stop command */
    MCPWM_TIMER_START_STOP_EMPTY, /*!< MCPWM timer starts counting and stops when next count reaches zero */
    MCPWM_TIMER_START_STOP_FULL,  /*!< MCPWM timer starts counting and stops when next count reaches peak */
} mcpwm_timer_start_stop_cmd_t;

[Honzik321]

After conducting tests with the oscilloscope, I identified an issue with the generation of the carrier frequency. There are two problems:
1. The first carrier pulse must be mandatorily set with minimum width of 1 μs.
2. The carrier frequency output is not perfectly time-synchronized—it slightly "drifts" within the 1 μs interval. This causes an inability to set an integral number of pulses (sometimes a portion of the last pulse is cut off).

I am currently addressing this issue without using the carrier frequency by setting one of the PWMs to a 1 μs period for generating a 1 MHz SCLK. With this approach, the issue of inaccurate synchronization does not occur. However, the drawback of this solution is that it does not allow for setting the CS low-to-SCLK delay and the SCLK stop-to-CS high delay, and the SCLK runs continuously.

[ok-home]

After conducting tests with the oscilloscope, I identified an issue with the generation of the carrier frequency. There are two problems:
1. The first carrier pulse must be mandatorily set with minimum width of 1 μs.
2. The carrier frequency output is not perfectly time-synchronized—it slightly "drifts" within the 1 μs interval. This causes an inability to set an integral number of pulses (sometimes a portion of the last pulse is cut off).

Indeed, the carrier prescaler is not synchronized ((

I am currently addressing this issue without using the carrier frequency by setting one of the PWMs to a 1 μs period for generating a 1 MHz SCLK. With this approach, the issue of inaccurate synchronization does not occur. However, the drawback of this solution is that it does not allow for setting the CS low-to-SCLK delay and the SCLK stop-to-CS high delay, and the SCLK runs continuously.

maybe it is enough to invert SCLK and / or change the pulse duty ?

[Honzik321]

I am reading data via SPI slave using the PWM synchronized generators (SCLK, CS). However, another issue has arisen. I need the CPU to be in light-sleep mode while the data from the SPI slave device is being filled into the RX buffers via DMA. However, PWM timers requires the APB clock to be enabled, meaning light-sleep cannot be used.
I will have to implement data acquisition from the SPI slave device using the ULP coprocessor. However, I am unsure whether it is possible to continuously read data into two ping-pong buffers via ULP using an interrupt triggered by the DRDY falling edge and wake up the main processor only when one of the buffers is full. I have no experience with ULP. It is possible to choose between two ULP options: FSM or RISC-V, but it seems that implementing what I need will not be easy.