Hi,
I wonder if it is possible to program the ESP32 in C/C++ without using any ESP specific or related library as I would like to control and sense a GPIO pin first and use interrupts and finally I would like to enable the wifi transmitter on a constant frequency (if possible) and then test it's transmission with a Software Defined Radio. I hear you asking 'why would you want to do this'? My answer is, I just want to learn the Xtensa processor to the register level. I also learned a Cortex-M3 uC this way which gave me a lot of satisfaction figuring out how to set system clocks and bridges and all kinds of registers just using pointers to absolute register addresses to begin with. It wonder if someone shares this passion...
Learning the Xtensa LX7 processor on a register level.
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- Posts: 9766
- Joined: Thu Nov 26, 2015 4:08 am
Re: Learning the Xtensa LX7 processor on a register level.
So two things in your way if you try that: 1. the Xtensa core lacks public documentation from its maker (Cadence); we have collected some public info here but it is lacking. 2. The WiFi register interface is closed; you only can use our (binary) drivers to talk to it.
For 1, there's a workaround in that you could decide to switch to the ESP32C3. That chip has a RiscV core that is publicly documented. The hardware WiFi interface of that still is not public, however.
For 1, there's a workaround in that you could decide to switch to the ESP32C3. That chip has a RiscV core that is publicly documented. The hardware WiFi interface of that still is not public, however.
Re: Learning the Xtensa LX7 processor on a register level.
Hi ESP_Sprite,
I'm glad I posted this question here and received your answer.
Thanks.
- I'm used to work with Cortex M3 uC with lots of information to the bare bone level of the uC
- I almost spend 3 days now browsing the Internet for espressif, xtensa and cadence and did not find anything usefull
- I did not find any pinout of the Xtensa uC
- I did not find any schematics on how the Xtensa uC is connected to the ESP32 pins (can be figured out just removing the cover)
- I did not find any information about the internal register addresses of the Xtensa uC
- I managed to control the GPIO pins high low state by directly accessing the corresponding register at the absolute address 0x3ff44004 as it is defined in some header file
- I'm very disappointed that all this info is kept secret but I can understand
- I think I will quit investigating ESP for any further project as my curiosity has disappeared on this subject...
Thanks again.
I'm glad I posted this question here and received your answer.
Thanks.
- I'm used to work with Cortex M3 uC with lots of information to the bare bone level of the uC
- I almost spend 3 days now browsing the Internet for espressif, xtensa and cadence and did not find anything usefull
- I did not find any pinout of the Xtensa uC
- I did not find any schematics on how the Xtensa uC is connected to the ESP32 pins (can be figured out just removing the cover)
- I did not find any information about the internal register addresses of the Xtensa uC
- I managed to control the GPIO pins high low state by directly accessing the corresponding register at the absolute address 0x3ff44004 as it is defined in some header file
- I'm very disappointed that all this info is kept secret but I can understand
- I think I will quit investigating ESP for any further project as my curiosity has disappeared on this subject...
Thanks again.
-
- Posts: 9766
- Joined: Thu Nov 26, 2015 4:08 am
Re: Learning the Xtensa LX7 processor on a register level.
I think you misunderstand. The Xtensa core is an integral part of the ESP32, in the same way an ARM core is an integral part of a STM32 chip. If you open the module, you'll (most likely) see two chips indeed, but those chips are the ESP32 itself and a flash chip that contains your program. Schematics for that are generally public, here is a random one, for instance.
The 'Xtensa uC' core does not have registers that have specific addresses. If you want peripheral addresses, those are documented in the Technical Reference Manual (where you'll also find docs about the GPIO address you wrote to)- I did not find any information about the internal register addresses of the Xtensa uC
- I managed to control the GPIO pins high low state by directly accessing the corresponding register at the absolute address 0x3ff44004 as it is defined in some header file
Re: Learning the Xtensa LX7 processor on a register level.
Hi ESP_Sprite,
my inspiration has mostly returned,
thanks!
my inspiration has mostly returned,
thanks!
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