PeterR wrote: ↑Fri Jul 10, 2020 11:12 pm
GPIO17 is not suitable for WROVER & PSRAM users (& who would not want 4MB of RAM!) because ROM (?) locked GPIO17 as PSRAM CS.
How do we stand on GPIO16 citations?
On the WROVER IO17 is SRAM clock and IO16 is SRAM chip select. So both are out of the equation...
IO16 and IO17 are respectively EMAC_CLK_OUT and EMAC_CLK_OUT_180 (i.e. 180° phase shift or inverted clock) generated by the EMAC peripheral, while IO0 clock output is generated by the APLL.
Some early designs using GPIO0 as the clock output used external inverting buffer before the PHY. I don't know if this is to solve a timing issue internal to the ESP32 (APLL sync with the EMAC or MUX/GPIO propagation delay for example) or if this is to solve a potential "external" timing issue on the PCB, or even PHY-dependent. So I suspect one can't be sure which one of the two EMAC_CLK_OUT GPIO will work in advance.