What would you like to see in The Next Chip?

[jas39_]

Kudos for asking!
Opening up for input from all your customers like this is a bold move as what you get is a mixed bag of goodies without any commit to volumes.

Adding usb seems to be a done deal, but would it be possible to run it as a "Mass Storage Device" aka USB Memory? I have used that method in other projects to provide an easy path to loading/upgrading fw. Just connect it to a PC and copy paste a file.

[ESP_Sprite]

Kudos for asking!

Opening up for input from all your customers like this is a bold move as what you get is a mixed bag of goodies without any commit to volumes.

Aye, but it helps lots with regards to brainstorming. Also, while we obviously are very interested in customers who buy millions of our chips from a business perspective, we're also interested in seeing what people can do with our tech, and if a feature costs only a little to implement but makes a lot of people happy, we don't necessarily need it to also make us a guaranteed amount of money. Also note that the lack of commitment to order volumes from the people here is countered by a lack of a guarantee on our side that we'll implement any of the suggestions.

Adding usb seems to be a done deal, but would it be possible to run it as a "Mass Storage Device" aka USB Memory? I have used that method in other projects to provide an easy path to loading/upgrading fw. Just connect it to a PC and copy paste a file.

Not in the ROM bootloader, as this is somewhat of an iffy thing to implement, and when it's in the ROM you can't tweak it anymore if some OS decides to access the mass storage device in a slightly different way... as an example, the early NXP LPC chips had that and they were a pain in the proverbials to use on a Linux system because they didn't account for the way that would access the storage device. It's entirely possible to e.g. write a secondary bit of firmware that lives on a protected bit of flash that handles this task, however; this means you can't use mass storage for the first upload, but you can use it for all uploads after that.

[chegewara]

What I would like to see is 2 radio. Reasons:
- using WiFi + bt is pain now
- using bt + ble
- maybe one radio could be 5GHz capable

[chromebin]

I think a better ESP32 would be just that, a better, leaner device with perfected ADC and RTC, as price is still a major consideration. Two radios would also interest us (for ESPNOW).

But most of all, instead of cramming everything in a single device, why not have cheap I/O extenders which implement some a coherency protocol? TileLink comes to mind. Such an extender could do many things like touch, medium speed I/O and ADC conversion. May be low power too. That leaves things like raw processing power, memory and the radios with the ESP. And where a radio isn't necessary, they'd also be a mighty fine complement to a modest (but cheap) RISC-V MCU.

Extenders would much facilitate board-layout (as the ESP recommended location is in a corner).

[Vader_Mester]

I think the inclusion of a 6LoWpan radio interface would make it such a widely usable solution!

[ESP_Sprite]

But most of all, instead of cramming everything in a single device, why not have cheap I/O extenders which implement some a coherency protocol? TileLink comes to mind.

The problem mostly is pin usage and speed. TileLink is an on-chip communication protocol first and foremost. Now, nothing is stopping you from getting that out of the chip (I think, I can't recall any latency requirements), but that would require a good hundred GPIOs for all the signals. Alternatively, you'd use something serial (like PCIE) but then you suddenly have multiple GHz signals and need to worry about transceiver design and floorspace. Sure, you can also slow everything down and run it as a serial port of max 1MHz or so, but then you're in I2C/SPI range... and then, for external ADC/RTC/DAC/... it would make much more sense to just add an external I2C or SPI unit instead of developing specialized things with our own inter-chip protocol.

[Yordan]

I would like to see in the next chip :

1. additional 16 bit low noise ADC which detects very low signals ( like 5-10 mV or so ) on isolated channel.
2. separate/isolated I2C bus.
3. 32 IO free ports.

[ESP_Sprite]

I would like to see in the next chip :

2. separate/isolated I2C bus.

What do you mean by this? The ESP32 already has 2 I2C peripherals, why would you want a 'separate' 3rd? Or do you mean galvanically isolated?

[zinahe]

Hey all,

I spent the some time reading some of the suggestions in this forum. I have to say; it's absolutely amazing to see how each and everyone wants the next chip to suit their own needs. Not surprisingly in a million and one different ways. That's just basic Game Theory; nothing new.

Word of caution to Espressif; I hope you have heard of the story of "Frankenstein". Apparently, it was made of the "best" available parts.

However, the Instead of trying to cater to every outlandish idea, why not just provide some basic CPLD/FPGA fabric along with some "official" soft-cores; and now everybody can create their own "ideal" version to their hearts' content.

Cheers,

[ESP_Sprite]

To be fair, Frankensteins monster wasn't really too bad, it was the human population who couldn't live with him and shunned him. He was said to be a pretty sensitive one, and as the rules of storytelling implore, he reacted badly to being bullied by the townspeople. (Not sure how much sense that makes wrt the analogy of the next chip, but there you go.)

And obviously we know that people will suggest anything their next project just happens to use. That's why this thread is not a popularity contest; we use it to gauge peoples interest, perhaps see trends in what people see an use for. Every opinion of someone here is just an anecdote, but you can derive some information out of it.