About the CAN controller.

rudi ;-) · Postby **rudi ;-)** » Sun Nov 20, 2016 8:39 pm

WiFive wrote:I don't think you need to know about AMBA.

Did you try assuming register set is approx same as SJA1000?

http://lxr.free-electrons.com/source/dr ... /sja1000.h

exactly WiFive like jeroen spoke that esp32 CAN is compatible with SJA 1000 so i would try this.

i compare and try with this too

http://ftp.icpdas.com/pub/cd/nuwa-l/app/can/sja1000.h
ftp://builder.ics.p.lodz.pl/PLD/3.0/pac ... /sja1000.h

and OrtCAN - Open (Ocera) RT CAN Framework

https://sourceforge.net/p/ortcan/lincan ... /sja1000.h

https://sourceforge.net/p/ortcan/lincan ... ican_cl2.h

and one from own doings -

so we have more sourcen.

txs for your help

btw
a reference for a "working model" i will use parallel MCP2515 as controller and TJA 1050 as transceiver with two extra ESP32 Modul
and do step by step. think first this messaging - write value in register, read from register. simple things, then try protokoll the timing about write / read and so on. then doings in mesh with one ESP32 as CAN controller.

the plan is, a WebServer with an simple Desk APP and read CAN Data and set CAN CMD for simple things.

start with the base this week.

best wishes
rudi

btw: CAN 2.0 and small infos can found here

append here
Comparison of Event-Triggered and Time-Triggered Concepts

embedded_world_04_albert.pdf: (597.79 KiB) Downloaded 1499 times

teach & deeper
( Dipl.-Ing.Dr.techn.Roman Obermaisser SRC)

habil.pdf: (2.76 MiB) Downloaded 1372 times

online eBook

rudi ;-) · Postby **rudi ;-)** » Sun Nov 20, 2016 11:09 pm

ESP_Sprite wrote:
If you write to the CAN registers, you may get bitten by a SoC bug in the first revision of the silicon that's out now: if you write the registers too quickly, the 2nd write may be discarded. This can be alleviated by putting a volatile asm(("nop;nop;nop;nop;nop;nop;nop;nop;"); line between writes, if memory serves. I'm not sure if the CAN controller is affected by this, but it may be good to keep this in mind.

Cant wait:
Short Test, Write, Read, Clear DPORT_AHBLITE_MPU_TABLE_CAN_REG full normal.
Next Steps same things with exact timing and stress.
will update this next time..let it open.

rudi ;-) · Postby **rudi ;-)** » Mon Nov 21, 2016 4:43 am

rudi ;-) wrote:
second:
not sure,
we use the same BIT in same Register for two difference function?
or have we difference Register?
Can you point me to the Register Docu / MUX `?
Or small bug?

https://github.com/espressif/esp-idf/bl ... reg.h#L940
Code: Select all
..
#define DPORT_CAN_CLK_EN   (BIT(19))
https://github.com/espressif/esp-idf/bl ... reg.h#L974
Code: Select all
..
#define DPORT_CAN_RST      (BIT(19))
..

part one

Code: Select all


void reg_delay (void) {
	
	__asm__ __volatile__("nop;nop;nop;nop;nop;nop;nop;nop;");
	
}

Have not see in this moment that we have 2 difference Register for this

(DPORT_PERIP_CLK_EN_REG, DPORT_CAN_CLK_EN)
(DPORT_PERIP_RST_EN_REG, DPORT_CAN_RST)

: BIT_IDX.png (24.85 KiB) Viewed 29304 times

part two

simple test doings for WRITE/READ/CLEAR and so on.

pwr_on

Code: Select all


/*
 The controller is powered off until you tweak the correct bits in 
 DPORT_PERIP_CLK_EN_REG and DPORT_PERIP_RST_EN_REG to enable it.
*/

void can_pwr_on (void) {
	
	/* to do 
	DPORT_PERIP_CLK_EN_REG and DPORT_PERIP_RST_EN_REG enable bits
	*/
	
	SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_CAN_CLK_EN);
	reg_delay();
	
	SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_CAN_RST);
	reg_delay();
}

pwr_off

Code: Select all


void can_pwr_off (void) {
	
	/* to do 
	DPORT_PERIP_CLK_EN_REG and DPORT_PERIP_RST_EN_REG disable bits
	*/
	CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_CAN_CLK_EN);
	reg_delay();
	
	CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_CAN_RST);
    reg_delay();
	
	
}

read_pwr

Code: Select all


uint32_t can_pwr_read (void) {
	
	// WHICH BIT IDX ?
	// here a simple code
	// get later more prof..
	
	// to do: better named
	uint32_t testbit1 = 0;
	uint32_t testbit2 = 0;
	
	testbit1 = GET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_CAN_CLK_EN)  ;
	printf("testbit 1 CAN_CLK_EN = %d\r\n", testbit1);
	reg_delay();
	
	testbit2 =  GET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_CAN_RST)  ;
	printf("testbit 2 CAN_RST    = %d\r\n", testbit2);
	
	// to do:
	// better named
	
	return testbit1 + testbit2;
	
	}

write bit to register
( not named in test simple (BIT( 3 )) for PID 5 example ( get later right names )

Code: Select all

void writeRegister (void) {
	
	// PID 2 3 4 5 6 7
	// BIT 0 1 2 3 4 5
	
	// DPORT_AHBLITE_MPU_TABLE_X_REG bit
	
	// to do: BIT MASK FOR MPU_TABLE_CAN_REG
	// here simple for TEST BIT ( 3 )
	
	SET_PERI_REG_MASK(DPORT_AHBLITE_MPU_TABLE_CAN_REG, 3);
		
}

read bit from register
( not named in test simple (BIT( 3 ))

Code: Select all


int readRegister (void) {
	
	int testbit = 0;
	
	// PID 2 3 4 5 6 7
	// BIT 0 1 2 3 4 5
	
	// DPORT_AHBLITE_MPU_TABLE_X_REG bit
	    
	// to do: BIT MASK FOR MPU_TABLE_CAN_REG
	// here simple for TEST BIT ( 3 )
		
	testbit = GET_PERI_REG_MASK(DPORT_AHBLITE_MPU_TABLE_CAN_REG,3);
	
	// to do  
	// better named
	
	if (testbit==0) {
		return 0;
	} else {
		return 1;
	}
	
}

clear the bit in register

Code: Select all


void clearRegister (void){
	
	// PID 2 3 4 5 6 7
	// BIT 0 1 2 3 4 5
	
	// DPORT_AHBLITE_MPU_TABLE_X_REG bit
		
	CLEAR_PERI_REG_MASK(DPORT_AHBLITE_MPU_TABLE_CAN_REG, 3);

}

: READ_WRITE_READ_CLEAR.png (14.48 KiB) Viewed 29304 times

short test
Video result:

Video : ESP32 Rev 0 CAN -PART TWO- 21 Nov 2016 - unofficially custom code -

next step: ( ~ tuesday )
..on this code..
..
UART Fifo OVF ( > 1000x Messages )
INTR / ISR
..
..
MESH

best wishes
rudi

comcat · Postby **comcat** » Mon Nov 21, 2016 5:37 am

COOL

rudi ;-) · Postby **rudi ;-)** » Mon Nov 21, 2016 11:47 am

comcat wrote:COOL

no no - comcat - there is only simple step by step base and with willful mistake
example see the note about reg_delay();

Code: Select all

void writeRegister (void) {
    // PID 2 3 4 5 6 7
   // BIT 0 1 2 3 4 5
   
   // DPORT_AHBLITE_MPU_TABLE_X_REG bit
   
   // to do: BIT MASK FOR MPU_TABLE_CAN_REG
   // here simple for TEST BIT ( 3 )
   
   SET_PERI_REG_MASK(DPORT_AHBLITE_MPU_TABLE_CAN_REG, 3);
   // for tesing here is no     reg_delay();
}

Code: Select all


void clearRegister (void){
   
   // PID 2 3 4 5 6 7
   // BIT 0 1 2 3 4 5
   
   // DPORT_AHBLITE_MPU_TABLE_X_REG bit
      
   CLEAR_PERI_REG_MASK(DPORT_AHBLITE_MPU_TABLE_CAN_REG, 3);
   // for tesing here is no     reg_delay();

}

and perhabs because this was not done, we get mistake in the response / Write to register
but this is what jeroen suggest to do that we do a small delay by

Code: Select all

__asm__ __volatile__("nop;nop;nop;nop;nop;nop;nop;nop;");

here is example the mistake: 100x ( read, set, read, clear )
( video 2:10 to 2:15 )
missing the clear doing ( its a write! ) , perhabs cause we have not delay here:

: clear_miss_cause_without_delay.png (74.3 KiB) Viewed 29237 times

in the next part of code ( asap ) we do testing the delay and other checkings that we get nice results without mistakes.
and i am sure CAN works like a dream like i have test just in time

this was only a fast simple testing cause could not wait does we need the write delay, can we use others things and more.
note, the uart runs in a queue task, the next is using INT "ETS_CAN_INTR_SOURCE" too
we run here only as Task and the result - i like like it is with this result, we can only go better with using the INT

i try to make at next check with difference with checking and comparing old and new bit and a check for successfull write/clear
cause we need timestamp too, the bit goes in a struct and last in a type as "can_data"..
later more infos with code post and post to github

..christmas is soon..

best wishes
rudi

rudi ;-) · Postby **rudi ;-)** » Wed Nov 23, 2016 2:52 pm

ok folks,

register write, clear, read nice do now,

but i am honest, i have a problem just in time ( on work )
to understand the HW fifo / ringbuffer.
http://esp32.com/viewtopic.php?f=2&t=534

i cant flush, clear the bit, not sure, what i make wrong.
cause we need this later too in the CAN_LOW, CAN_HIGH
must understand first how it works and how to handle it.
--am at work on this --

btw here a fine log no mistake any more in quickly write/clear -

Code: Select all

testbit 1 CAN_CLK_EN = 0

testbit 2 CAN_RST    = 0

CAN Power : disabled


testbit 1 CAN_CLK_EN = 524288

testbit 2 CAN_RST    = 524288

CAN Power : enabled


       0: RegVal = 0

       1: RegVal = 1

--------------------

       2: RegVal = 0

       3: RegVal = 1

--------------------

       4: RegVal = 0

       5: RegVal = 1

--------------------

       6: RegVal = 0

       7: RegVal = 1

--------------------

       8: RegVal = 0

       9: RegVal = 1

--------------------

      10: RegVal = 0

      11: RegVal = 1

--------------------

      12: RegVal = 0

      13: RegVal = 1

--------------------

      14: RegVal = 0

      15: RegVal = 1

--------------------

      16: RegVal = 0

      17: RegVal = 1

--------------------

      18: RegVal = 0

      19: RegVal = 1

--------------------


      20: RegVal = 0

      21: RegVal = 1

--------------------

      22: RegVal = 0

      23: RegVal = 1

--------------------

      24: RegVal = 0

      25: RegVal = 1

--------------------

      26: RegVal = 0

      27: RegVal = 1

--------------------

      28: RegVal = 0

      29: RegVal = 1

--------------------

      30: RegVal = 0

      31: RegVal = 1

--------------------

      32: RegVal = 0

      33: RegVal = 1

--------------------

      34: RegVal = 0

      35: RegVal = 1

--------------------

      36: RegVal = 0

      37: RegVal = 1

--------------------

      38: RegVal = 0

      39: RegVal = 1

--------------------

      40: RegVal = 0

      41: RegVal = 1

--------------------

      42: RegVal = 0

      43: RegVal = 1

--------------------

      44: RegVal = 0

      45: RegVal = 1

--------------------

      46: RegVal = 0

      47: RegVal = 1

--------------------

      48: RegVal = 0

      49: RegVal = 1

--------------------

      50: RegVal = 0

      51: RegVal = 1

--------------------

      52: RegVal = 0

      53: RegVal = 1

--------------------

      54: RegVal = 0

      55: RegVal = 1

--------------------

      56: RegVal = 0

      57: RegVal = 1

--------------------

      58: RegVal = 0

      59: RegVal = 1

--------------------

      60: RegVal = 0

      61: RegVal = 1

--------------------

      62: RegVal = 0

      63: RegVal = 1

--------------------

      64: RegVal = 0

      65: RegVal = 1

--------------------

      66: RegVal = 0

      67: RegVal = 1

--------------------

      68: RegVal = 0

      69: RegVal = 1

--------------------

      70: RegVal = 0

      71: RegVal = 1

--------------------

      72: RegVal = 0

      73: RegVal = 1

--------------------

      74: RegVal = 0

      75: RegVal = 1

--------------------

      76: RegVal = 0

      77: RegVal = 1

--------------------

      78: RegVal = 0

      79: RegVal = 1

--------------------

      80: RegVal = 0

      81: RegVal = 1

--------------------

      82: RegVal = 0

      83: RegVal = 1

--------------------

      84: RegVal = 0

      85: RegVal = 1

--------------------

      86: RegVal = 0

      87: RegVal = 1

--------------------

      88: RegVal = 0

      89: RegVal = 1

--------------------

      90: RegVal = 0

      91: RegVal = 1

--------------------

      92: RegVal = 0

      93: RegVal = 1

--------------------

      94: RegVal = 0

      95: RegVal = 1

--------------------

      96: RegVal = 0

      97: RegVal = 1

--------------------

      98: RegVal = 0

      99: RegVal = 1

--------------------

     100: RegVal = 0

     101: RegVal = 1

--------------------

     102: RegVal = 0

     103: RegVal = 1

--------------------

     104: RegVal = 0

     105: RegVal = 1

--------------------

     106: RegVal = 0

     107: RegVal = 1

--------------------

     108: RegVal = 0

     109: RegVal = 1

--------------------

     110: RegVal = 0

     111: RegVal = 1

--------------------

     112: RegVal = 0

     113: RegVal = 1

--------------------

     114: RegVal = 0

     115: RegVal = 1

--------------------

     116: RegVal = 0

     117: RegVal = 1

--------------------

     118: RegVal = 0

     119: RegVal = 1

--------------------

     120: RegVal = 0

     121: RegVal = 1

--------------------

     122: RegVal = 0

     123: RegVal = 1

--------------------

     124: RegVal = 0

     125: RegVal = 1

--------------------

     126: RegVal = 0

     127: RegVal = 1

--------------------

     128: RegVal = 0

     129: RegVal = 1

--------------------

     130: RegVal = 0

     131: RegVal = 1

--------------------

     132: RegVal = 0

     133: RegVal = 1

--------------------

     134: RegVal = 0

     135: RegVal = 0

     136: RegVal = 0

     137: RegVal = 1

--------------------

     138: RegVal = 0

     139: RegVal = 1

--------------------

     140: RegVal = 0

     141: RegVal = 1

--------------------

     142: RegVal = 0

     143: RegVal = 1

--------------------

     144: RegVal = 0

     145: RegVal = 1

--------------------

     146: RegVal = 0

     147: RegVal = 1

--------------------

     148: RegVal = 0

     149: RegVal = 1

--------------------

     150: RegVal = 0

     151: RegVal = 1

--------------------

     152: RegVal = 0

     153: RegVal = 1

--------------------

     154: RegVal = 0

     155: RegVal = 1

--------------------

     156: RegVal = 0

     157: RegVal = 1

--------------------

     158: RegVal = 0

     159: RegVal = 1

--------------------

     160: RegVal = 0

     161: RegVal = 1

--------------------

     162: RegVal = 0

     163: RegVal = 1

--------------------

     164: RegVal = 0

     165: RegVal = 1

--------------------

     166: RegVal = 0

     167: RegVal = 1

--------------------

     168: RegVal = 0

     169: RegVal = 1

--------------------

     170: RegVal = 0

     171: RegVal = 1

--------------------

     172: RegVal = 0

     173: RegVal = 1

--------------------

     174: RegVal = 0

     175: RegVal = 1

--------------------

     176: RegVal = 0

     177: RegVal = 1

--------------------

     178: RegVal = 0

     179: RegVal = 1

--------------------

     180: RegVal = 0

     181: RegVal = 1

--------------------

     182: RegVal = 0

     183: RegVal = 1

--------------------

     184: RegVal = 0

     185: RegVal = 1

--------------------

     186: RegVal = 0

     187: RegVal = 1

--------------------

     188: RegVal = 0

     189: RegVal = 1

--------------------

     190: RegVal = 0

     191: RegVal = 1

--------------------

     192: RegVal = 0

     193: RegVal = 1

--------------------

     194: RegVal = 0

     195: RegVal = 1

--------------------

     196: RegVal = 0

     197: RegVal = 1

--------------------

     198: RegVal = 0

     199: RegVal = 1

--------------------

     200: RegVal = 0

     201: RegVal = 1

--------------------

     202: RegVal = 0

     203: RegVal = 1

--------------------

     204: RegVal = 0

     205: RegVal = 1

--------------------

     206: RegVal = 0

     207: RegVal = 1

--------------------

     208: RegVal = 0

     209: RegVal = 1

--------------------

     210: RegVal = 0

     211: RegVal = 1

--------------------

     212: RegVal = 0

     213: RegVal = 1

--------------------

     214: RegVal = 0

     215: RegVal = 1

--------------------

     216: RegVal = 0

     217: RegVal = 1

--------------------

     218: RegVal = 0

     219: RegVal = 1

--------------------

     220: RegVal = 0

     221: RegVal = 1

--------------------

     222: RegVal = 0

     223: RegVal = 1

--------------------

     224: RegVal = 0

     225: RegVal = 1

--------------------

     226: RegVal = 0

     227: RegVal = 1

--------------------

     228: RegVal = 0

     229: RegVal = 1

--------------------

     230: RegVal = 0

     231: RegVal = 1

--------------------

     232: RegVal = 0

     233: RegVal = 1

--------------------

     234: RegVal = 0

     235: RegVal = 1

--------------------

     236: RegVal = 0

     237: RegVal = 1

--------------------

     238: RegVal = 0

     239: RegVal = 1

--------------------

     240: RegVal = 0

     241: RegVal = 1

--------------------

     242: RegVal = 0

     243: RegVal = 1

--------------------

     244: RegVal = 0

     245: RegVal = 1

--------------------

     246: RegVal = 0

     247: RegVal = 1

--------------------

     248: RegVal = 0

     249: RegVal = 1

--------------------

     250: RegVal = 0

     251: RegVal = 1

--------------------

     252: RegVal = 0

     253: RegVal = 1

--------------------

     254: RegVal = 0

     255: RegVal = 1

--------------------

     256: RegVal = 0

     257: RegVal = 1

--------------------

     258: RegVal = 0

     259: RegVal = 1

--------------------

     260: RegVal = 0

     261: RegVal = 1

--------------------

     262: RegVal = 0

     263: RegVal = 1

--------------------

     264: RegVal = 0

     265: RegVal = 1

--------------------

     266: RegVal = 0

     267: RegVal = 1

--------------------

     268: RegVal = 0

     269: RegVal = 1

--------------------

     270: RegVal = 0

     271: RegVal = 1

--------------------

     272: RegVal = 0

     273: RegVal = 1

--------------------

     274: RegVal = 0

     275: RegVal = 1

--------------------

     276: RegVal = 0

     277: RegVal = 1

--------------------

     278: RegVal = 0

     279: RegVal = 1

--------------------

     280: RegVal = 0

     281: RegVal = 1

--------------------

     282: RegVal = 0

     283: RegVal = 1

--------------------

     284: RegVal = 0

     285: RegVal = 1

--------------------

     286: RegVal = 0

     287: RegVal = 1

--------------------

     288: RegVal = 0

     289: RegVal = 1

--------------------

     290: RegVal = 0

     291: RegVal = 1

--------------------

     292: RegVal = 0

     293: RegVal = 1

--------------------

     294: RegVal = 0

     295: RegVal = 1

--------------------

     296: RegVal = 0

     297: RegVal = 1

--------------------

     298: RegVal = 0

     299: RegVal = 1

--------------------

     300: RegVal = 0

     301: RegVal = 1

--------------------

     302: RegVal = 0

     303: RegVal = 1

--------------------

     304: RegVal = 0

     305: RegVal = 1

--------------------

     306: RegVal = 0

     307: RegVal = 1

--------------------

     308: RegVal = 0

     309: RegVal = 1

--------------------

     310: RegVal = 0

     311: RegVal = 1

--------------------

     312: RegVal = 0

     313: RegVal = 1

--------------------

     314: RegVal = 0

     315: RegVal = 1

--------------------

     316: RegVal = 0

     317: RegVal = 1

--------------------

     318: RegVal = 0

     319: RegVal = 1

--------------------

     320: RegVal = 0

     321: RegVal = 1

--------------------

     322: RegVal = 0

     323: RegVal = 1

--------------------

     324: RegVal = 0

     325: RegVal = 1

--------------------

     326: RegVal = 0

     327: RegVal = 1

--------------------

     328: RegVal = 0

     329: RegVal = 1

--------------------

     330: RegVal = 0

     331: RegVal = 1

--------------------

     332: RegVal = 0

     333: RegVal = 1

--------------------

     334: RegVal = 0

     335: RegVal = 1

--------------------

     336: RegVal = 0

     337: RegVal = 1

--------------------

     338: RegVal = 0

     339: RegVal = 1

--------------------

     340: RegVal = 0

     341: RegVal = 1

--------------------

     342: RegVal = 0

     343: RegVal = 1

--------------------

     344: RegVal = 0

     345: RegVal = 1

--------------------

     346: RegVal = 0

     347: RegVal = 1

--------------------

     348: RegVal = 0

     349: RegVal = 1

--------------------

     350: RegVal = 0

     351: RegVal = 1

--------------------

     352: RegVal = 0

     353: RegVal = 1

--------------------

     354: RegVal = 0

     355: RegVal = 1

--------------------

     356: RegVal = 0

     357: RegVal = 1

--------------------

     358: RegVal = 0

     359: RegVal = 1

--------------------

     360: RegVal = 0

     361: RegVal = 1

--------------------

     362: RegVal = 0

     363: RegVal = 1

--------------------

     364: RegVal = 0

     365: RegVal = 1

--------------------

     366: RegVal = 0

     367: RegVal = 1

--------------------

     368: RegVal = 0

     369: RegVal = 1

--------------------

     370: RegVal = 0

     371: RegVal = 1

--------------------

     372: RegVal = 0

     373: RegVal = 1

--------------------

     374: RegVal = 0

     375: RegVal = 1

--------------------

     376: RegVal = 0

     377: RegVal = 1

--------------------

     378: RegVal = 0

     379: RegVal = 1

--------------------

     380: RegVal = 0

     381: RegVal = 1

--------------------

     382: RegVal = 0

     383: RegVal = 1

--------------------

     384: RegVal = 0

     385: RegVal = 1

--------------------

     386: RegVal = 0

     387: RegVal = 1

--------------------

     388: RegVal = 0

     389: RegVal = 1

--------------------

     390: RegVal = 0

     391: RegVal = 1

--------------------

     392: RegVal = 0

     393: RegVal = 1

--------------------

     394: RegVal = 0

     395: RegVal = 1

--------------------

     396: RegVal = 0

     397: RegVal = 1

--------------------

     398: RegVal = 0

     399: RegVal = 1

--------------------

     400: RegVal = 0

     401: RegVal = 1

--------------------

     402: RegVal = 0

     403: RegVal = 1

--------------------

     404: RegVal = 0

     405: RegVal = 1

--------------------

     406: RegVal = 0

     407: RegVal = 1

--------------------

     408: RegVal = 0

     409: RegVal = 1

--------------------

     410: RegVal = 0

     411: RegVal = 1

--------------------

     412: RegVal = 0

     413: RegVal = 1

--------------------

     414: RegVal = 0

     415: RegVal = 1

--------------------

     416: RegVal = 0

     417: RegVal = 1

--------------------

     418: RegVal = 0

     419: RegVal = 1

--------------------

     420: RegVal = 0

     421: RegVal = 1

--------------------

     422: RegVal = 0

     423: RegVal = 1

--------------------

     424: RegVal = 0

     425: RegVal = 1

--------------------

     426: RegVal = 0

     427: RegVal = 1

--------------------

     428: RegVal = 0

     429: RegVal = 1

--------------------

     430: RegVal = 0

     431: RegVal = 1

--------------------

     432: RegVal = 0

     433: RegVal = 1

--------------------

     434: RegVal = 0

     435: RegVal = 1

--------------------

     436: RegVal = 0

     437: RegVal = 1

--------------------

     438: RegVal = 0

     439: RegVal = 1

--------------------

     440: RegVal = 0

     441: RegVal = 1

--------------------

     442: RegVal = 0

     443: RegVal = 1

--------------------

     444: RegVal = 0

     445: RegVal = 1

--------------------

     446: RegVal = 0

     447: RegVal = 1

--------------------

     448: RegVal = 0

     449: RegVal = 1

--------------------

     450: RegVal = 0

     451: RegVal = 1

--------------------

     452: RegVal = 0

     453: RegVal = 1

--------------------

     454: RegVal = 0

     455: RegVal = 1

--------------------

     456: RegVal = 0

     457: RegVal = 1

--------------------

     458: RegVal = 0

     459: RegVal = 1

--------------------

     460: RegVal = 0

     461: RegVal = 1

--------------------

     462: RegVal = 0

     463: RegVal = 1

--------------------

     464: RegVal = 0

     465: RegVal = 1

--------------------

     466: RegVal = 0

     467: RegVal = 1

--------------------

     468: RegVal = 0

     469: RegVal = 1

--------------------

     470: RegVal = 0

     471: RegVal = 1

--------------------

     472: RegVal = 0

     473: RegVal = 1

--------------------

     474: RegVal = 0

     475: RegVal = 1

--------------------

     476: RegVal = 0

     477: RegVal = 1

--------------------

     478: RegVal = 0

     479: RegVal = 1

--------------------

     480: RegVal = 0

     481: RegVal = 1

--------------------

     482: RegVal = 0

     483: RegVal = 1

--------------------

     484: RegVal = 0

     485: RegVal = 1

--------------------

     486: RegVal = 0

     487: RegVal = 1

--------------------

     488: RegVal = 0

     489: RegVal = 1

--------------------

     490: RegVal = 0

     491: RegVal = 1

--------------------

     492: RegVal = 0

     493: RegVal = 1

--------------------

     494: RegVal = 0

     495: RegVal = 1

--------------------

     496: RegVal = 0

     497: RegVal = 1

--------------------

     498: RegVal = 0

     499: RegVal = 1

--------------------

     500: RegVal = 0

     501: RegVal = 1

--------------------

     502: RegVal = 0

     503: RegVal = 1

--------------------

     504: RegVal = 0

     505: RegVal = 1

--------------------

     506: RegVal = 0

     507: RegVal = 1

--------------------

     508: RegVal = 0

     509: RegVal = 1

--------------------

     510: RegVal = 0

     511: RegVal = 1

--------------------

     512: RegVal = 0

     513: RegVal = 1

--------------------

     514: RegVal = 0

     515: RegVal = 1

--------------------

     516: RegVal = 0

     517: RegVal = 1

--------------------

     518: RegVal = 0

     519: RegVal = 1

--------------------

     520: RegVal = 0

     521: RegVal = 1

--------------------

     522: RegVal = 0

     523: RegVal = 1

--------------------

     524: RegVal = 0

     525: RegVal = 1

--------------------

     526: RegVal = 0

     527: RegVal = 1

--------------------

     528: RegVal = 0

     529: RegVal = 1

--------------------

     530: RegVal = 0

     531: RegVal = 0

     532: RegVal = 0

     533: RegVal = 1

--------------------

     534: RegVal = 0

     535: RegVal = 1

--------------------

     536: RegVal = 0

     537: RegVal = 1

--------------------

     538: RegVal = 0

     539: RegVal = 1

--------------------

     540: RegVal = 0

     541: RegVal = 1

--------------------

     542: RegVal = 0

     543: RegVal = 1

--------------------

     544: RegVal = 0

     545: RegVal = 1

--------------------

     546: RegVal = 0

     547: RegVal = 1

--------------------

     548: RegVal = 0

     549: RegVal = 1

--------------------

     550: RegVal = 0

     551: RegVal = 1

--------------------

     552: RegVal = 0

     553: RegVal = 1

--------------------

     554: RegVal = 0

     555: RegVal = 1

--------------------

     556: RegVal = 0

     557: RegVal = 1

--------------------

     558: RegVal = 0

     559: RegVal = 1

--------------------

     560: RegVal = 0

     561: RegVal = 1

--------------------

     562: RegVal = 0

     563: RegVal = 1

--------------------

     564: RegVal = 0

     565: RegVal = 1

--------------------

     566: RegVal = 0

     567: RegVal = 1

--------------------

     568: RegVal = 0

     569: RegVal = 1

--------------------

     570: RegVal = 0

     571: RegVal = 1

--------------------

     572: RegVal = 0

     573: RegVal = 1

--------------------

     574: RegVal = 0

     575: RegVal = 1

--------------------

     576: RegVal = 0

     577: RegVal = 1

--------------------

     578: RegVal = 0

     579: RegVal = 1

--------------------

     580: RegVal = 0

     581: RegVal = 1

--------------------

     582: RegVal = 0

     583: RegVal = 1

--------------------

     584: RegVal = 0

     585: RegVal = 1

--------------------

     586: RegVal = 0

     587: RegVal = 1

--------------------

     588: RegVal = 0

     589: RegVal = 1

--------------------

     590: RegVal = 0

     591: RegVal = 1

--------------------

     592: RegVal = 0

     593: RegVal = 1

--------------------

     594: RegVal = 0

     595: RegVal = 1

--------------------

     596: RegVal = 0

     597: RegVal = 1

--------------------

     598: RegVal = 0

     599: RegVal = 1

--------------------

     600: RegVal = 0

     601: RegVal = 1

--------------------

     602: RegVal = 0

     603: RegVal = 1

--------------------

     604: RegVal = 0

     605: RegVal = 1

--------------------

     606: RegVal = 0

     607: RegVal = 1

--------------------

     608: RegVal = 0

     609: RegVal = 1

--------------------

     610: RegVal = 0

     611: RegVal = 1

--------------------

     612: RegVal = 0

     613: RegVal = 1

--------------------

     614: RegVal = 0

     615: RegVal = 1

--------------------

     616: RegVal = 0

     617: RegVal = 1

--------------------

     618: RegVal = 0

     619: RegVal = 1

--------------------

     620: RegVal = 0

     621: RegVal = 1

--------------------

     622: RegVal = 0

     623: RegVal = 1

--------------------

     624: RegVal = 0

     625: RegVal = 1

--------------------

     626: RegVal = 0

     627: RegVal = 1

--------------------

     628: RegVal = 0

     629: RegVal = 1

--------------------

     630: RegVal = 0

     631: RegVal = 1

--------------------

     632: RegVal = 0

     633: RegVal = 1

--------------------

     634: RegVal = 0

     635: RegVal = 1

--------------------

     636: RegVal = 0

     637: RegVal = 1

--------------------

     638: RegVal = 0

     639: RegVal = 1

--------------------

     640: RegVal = 0

     641: RegVal = 1

--------------------

     642: RegVal = 0

     643: RegVal = 1

--------------------

     644: RegVal = 0

     645: RegVal = 1

--------------------

     646: RegVal = 0

     647: RegVal = 1

--------------------

     648: RegVal = 0

     649: RegVal = 1

--------------------

     650: RegVal = 0

     651: RegVal = 1

--------------------

     652: RegVal = 0

     653: RegVal = 1

--------------------

     654: RegVal = 0

     655: RegVal = 1

--------------------

     656: RegVal = 0

     657: RegVal = 1

--------------------

     658: RegVal = 0

     659: RegVal = 1

--------------------

     660: RegVal = 0

     661: RegVal = 1

--------------------

     662: RegVal = 0

     663: RegVal = 1

--------------------

     664: RegVal = 0

     665: RegVal = 1

--------------------

     666: RegVal = 0

     667: RegVal = 1

--------------------

     668: RegVal = 0

     669: RegVal = 1

--------------------

     670: RegVal = 0

     671: RegVal = 1

--------------------

     672: RegVal = 0

     673: RegVal = 1

--------------------

     674: RegVal = 0

     675: RegVal = 1

--------------------

     676: RegVal = 0

     677: RegVal = 1

--------------------

     678: RegVal = 0

     679: RegVal = 1

--------------------

     680: RegVal = 0

     681: RegVal = 1

--------------------

     682: RegVal = 0

     683: RegVal = 1

--------------------

     684: RegVal = 0

     685: RegVal = 1

--------------------

     686: RegVal = 0

     687: RegVal = 1

--------------------

     688: RegVal = 0

     689: RegVal = 1

--------------------

     690: RegVal = 0

     691: RegVal = 1

--------------------

     692: RegVal = 0

     693: RegVal = 1

--------------------

     694: RegVal = 0

     695: RegVal = 1

--------------------

     696: RegVal = 0

     697: RegVal = 1

--------------------

     698: RegVal = 0

     699: RegVal = 1

--------------------

     700: RegVal = 0

     701: RegVal = 1

--------------------

     702: RegVal = 0

     703: RegVal = 1

--------------------

     704: RegVal = 0

     705: RegVal = 1

--------------------

     706: RegVal = 0

     707: RegVal = 1

--------------------

     708: RegVal = 0

     709: RegVal = 1

--------------------

     710: RegVal = 0

     711: RegVal = 1

--------------------

     712: RegVal = 0

     713: RegVal = 1

--------------------

     714: RegVal = 0

     715: RegVal = 1

--------------------

     716: RegVal = 0

     717: RegVal = 1

--------------------

     718: RegVal = 0

     719: RegVal = 1

--------------------

     720: RegVal = 0

     721: RegVal = 1

--------------------

     722: RegVal = 0

     723: RegVal = 1

--------------------

     724: RegVal = 0

     725: RegVal = 1

--------------------

     726: RegVal = 0

     727: RegVal = 1

--------------------

     728: RegVal = 0

     729: RegVal = 1

--------------------

     730: RegVal = 0

     731: RegVal = 1

--------------------

     732: RegVal = 0

     733: RegVal = 1

--------------------

     734: RegVal = 0

     735: RegVal = 1

--------------------

     736: RegVal = 0

     737: RegVal = 1

--------------------

     738: RegVal = 0

     739: RegVal = 1

--------------------

     740: RegVal = 0

     741: RegVal = 1

--------------------

     742: RegVal = 0

     743: RegVal = 1

--------------------

     744: RegVal = 0

     745: RegVal = 1

--------------------

     746: RegVal = 0

     747: RegVal = 1

--------------------

     748: RegVal = 0

     749: RegVal = 1

--------------------

     750: RegVal = 0

     751: RegVal = 1

--------------------

     752: RegVal = 0

     753: RegVal = 1

--------------------

     754: RegVal = 1

--------------------

     755: RegVal = 0

     756: RegVal = 1

--------------------

     757: RegVal = 0

     758: RegVal = 1

--------------------

     759: RegVal = 0

     760: RegVal = 1

--------------------

     761: RegVal = 0

     762: RegVal = 1

--------------------

     763: RegVal = 0

     764: RegVal = 1

--------------------

     765: RegVal = 0

     766: RegVal = 1

--------------------

     767: RegVal = 0

     768: RegVal = 1

--------------------

     769: RegVal = 0

     770: RegVal = 1

--------------------

     771: RegVal = 0

     772: RegVal = 1

--------------------

     773: RegVal = 0

     774: RegVal = 1

--------------------

     775: RegVal = 0

     776: RegVal = 1

--------------------

     777: RegVal = 0

     778: RegVal = 1

--------------------

     779: RegVal = 0

     780: RegVal = 1

--------------------

     781: RegVal = 0

     782: RegVal = 1

--------------------

     783: RegVal = 0

     784: RegVal = 1

--------------------

     785: RegVal = 0

     786: RegVal = 1

--------------------

     787: RegVal = 0

     788: RegVal = 1

--------------------

     789: RegVal = 0

     790: RegVal = 1

--------------------

     791: RegVal = 0

     792: RegVal = 1

--------------------

     793: RegVal = 0

     794: RegVal = 1

--------------------

     795: RegVal = 0

     796: RegVal = 1

--------------------

     797: RegVal = 0

     798: RegVal = 1

--------------------

     799: RegVal = 0

     800: RegVal = 1

--------------------

     801: RegVal = 0

     802: RegVal = 1

--------------------

     803: RegVal = 0

     804: RegVal = 1

--------------------

     805: RegVal = 0

     806: RegVal = 1

--------------------

     807: RegVal = 0

     808: RegVal = 1

--------------------

     809: RegVal = 0

     810: RegVal = 1

--------------------

     811: RegVal = 0

     812: RegVal = 1

--------------------

     813: RegVal = 0

     814: RegVal = 1

--------------------

     815: RegVal = 0

     816: RegVal = 1

--------------------

     817: RegVal = 0

     818: RegVal = 1

--------------------

     819: RegVal = 0

     820: RegVal = 1

--------------------

     821: RegVal = 0

     822: RegVal = 1

--------------------

     823: RegVal = 0

     824: RegVal = 1

--------------------

     825: RegVal = 0

     826: RegVal = 1

--------------------

     827: RegVal = 0

     828: RegVal = 1

--------------------

     829: RegVal = 0

     830: RegVal = 1

--------------------

     831: RegVal = 0

     832: RegVal = 1

--------------------

     833: RegVal = 0

     834: RegVal = 1

--------------------

     835: RegVal = 0

     836: RegVal = 1

--------------------

     837: RegVal = 0

     838: RegVal = 1

--------------------

     839: RegVal = 0

     840: RegVal = 1

--------------------

     841: RegVal = 0

     842: RegVal = 1

--------------------

     843: RegVal = 0

     844: RegVal = 1

--------------------

     845: RegVal = 0

     846: RegVal = 1

--------------------

     847: RegVal = 0

     848: RegVal = 1

--------------------

     849: RegVal = 0

     850: RegVal = 1

--------------------

     851: RegVal = 0

     852: RegVal = 1

--------------------

     853: RegVal = 0

     854: RegVal = 1

--------------------

     855: RegVal = 0

     856: RegVal = 1

--------------------

     857: RegVal = 0

     858: RegVal = 1

--------------------

     859: RegVal = 0

     860: RegVal = 1

--------------------

     861: RegVal = 0

     862: RegVal = 1

--------------------

     863: RegVal = 0

     864: RegVal = 1

--------------------

     865: RegVal = 0

     866: RegVal = 1

--------------------

     867: RegVal = 0

     868: RegVal = 1

--------------------

     869: RegVal = 0

     870: RegVal = 1

--------------------

     871: RegVal = 0

     872: RegVal = 1

--------------------

     873: RegVal = 0

     874: RegVal = 1

--------------------

     875: RegVal = 0

     876: RegVal = 1

--------------------

     877: RegVal = 0

     878: RegVal = 1

--------------------

     879: RegVal = 0

     880: RegVal = 1

--------------------

     881: RegVal = 0

     882: RegVal = 1

--------------------

     883: RegVal = 0

     884: RegVal = 1

--------------------

     885: RegVal = 0

     886: RegVal = 1

--------------------

     887: RegVal = 0

     888: RegVal = 1

--------------------

     889: RegVal = 0

     890: RegVal = 1

--------------------

     891: RegVal = 0

     892: RegVal = 1

--------------------

     893: RegVal = 0

     894: RegVal = 1

--------------------

     895: RegVal = 0

     896: RegVal = 1

--------------------

     897: RegVal = 0

     898: RegVal = 1

--------------------

     899: RegVal = 0

     900: RegVal = 1

--------------------

     901: RegVal = 0

     902: RegVal = 1

--------------------

     903: RegVal = 0

     904: RegVal = 1

--------------------

     905: RegVal = 0

     906: RegVal = 1

--------------------

     907: RegVal = 0

     908: RegVal = 1

--------------------

     909: RegVal = 0

     910: RegVal = 1

--------------------

     911: RegVal = 0

     912: RegVal = 1

--------------------

     913: RegVal = 0

     914: RegVal = 1

--------------------

     915: RegVal = 0

     916: RegVal = 1

--------------------

     917: RegVal = 0

     918: RegVal = 1

--------------------

     919: RegVal = 0

     920: RegVal = 1

--------------------

     921: RegVal = 0

     922: RegVal = 1

--------------------

     923: RegVal = 0

     924: RegVal = 1

--------------------

     925: RegVal = 0

     926: RegVal = 1

--------------------

     927: RegVal = 0

     928: RegVal = 1

--------------------

     929: RegVal = 0

     930: RegVal = 1

--------------------

     931: RegVal = 0

     932: RegVal = 1

--------------------

     933: RegVal = 0

     934: RegVal = 1

--------------------

     935: RegVal = 0

     936: RegVal = 1

--------------------

     937: RegVal = 0

     938: RegVal = 1

--------------------

     939: RegVal = 0

     940: RegVal = 1

--------------------

     941: RegVal = 0

     942: RegVal = 1

--------------------

     943: RegVal = 0

     944: RegVal = 1

--------------------

     945: RegVal = 0

     946: RegVal = 1

--------------------

     947: RegVal = 0

     948: RegVal = 1

--------------------

     949: RegVal = 0

     950: RegVal = 1

--------------------

     951: RegVal = 0

     952: RegVal = 1

--------------------

     953: RegVal = 0

     954: RegVal = 1

--------------------

     955: RegVal = 0

     956: RegVal = 1

--------------------

     957: RegVal = 0

     958: RegVal = 1

--------------------

     959: RegVal = 0

     960: RegVal = 1

--------------------

     961: RegVal = 0

     962: RegVal = 1

--------------------

     963: RegVal = 0

     964: RegVal = 1

--------------------

     965: RegVal = 0

     966: RegVal = 1

--------------------

     967: RegVal = 0

     968: RegVal = 1

--------------------

     969: RegVal = 0

     970: RegVal = 1

--------------------

     971: RegVal = 0

     972: RegVal = 1

--------------------

     973: RegVal = 0

     974: RegVal = 1

--------------------

     975: RegVal = 0

     976: RegVal = 1

--------------------

     977: RegVal = 0

     978: RegVal = 1

--------------------

     979: RegVal = 0

     980: RegVal = 1

--------------------

     981: RegVal = 0

     982: RegVal = 1

--------------------

     983: RegVal = 0

     984: RegVal = 1

--------------------

     985: RegVal = 0

     986: RegVal = 1

--------------------

     987: RegVal = 0

     988: RegVal = 1

--------------------

     989: RegVal = 0

     990: RegVal = 1

--------------------

     991: RegVal = 0

     992: RegVal = 1

--------------------

     993: RegVal = 0

     994: RegVal = 1

--------------------

     995: RegVal = 0

     996: RegVal = 1

--------------------

     997: RegVal = 0

     998: RegVal = 1

--------------------

     999: RegVal = 0

    1000: RegVal = 1

--------------------

    1001: RegVal = 0

    1002: RegVal = 1

--------------------

    1003: RegVal = 0

    1004: RegVal = 1

--------------------

    1005: RegVal = 0

    1006: RegVal = 1

--------------------

    1007: RegVal = 0

    1008: RegVal = 1

--------------------

    1009: RegVal = 0

    1010: RegVal = 1

--------------------

    1011: RegVal = 0

    1012: RegVal = 1

--------------------

    1013: RegVal = 0

    1014: RegVal = 1

--------------------

    1015: RegVal = 0

    1016: RegVal = 1

--------------------

    1017: RegVal = 0

    1018: RegVal = 1

--------------------

    1019: RegVal = 0

    1020: RegVal = 1

--------------------

    1021: RegVal = 0

    1022: RegVal = 1

--------------------

    1023: RegVal = 0

    1024: RegVal = 1

--------------------

    1025: RegVal = 0

    1026: RegVal = 1

--------------------

    1027: RegVal = 0

    1028: RegVal = 1

--------------------

    1029: RegVal = 0

    1030: RegVal = 1

--------------------

    1031: RegVal = 0

    1032: RegVal = 1

--------------------

    1033: RegVal = 0

    1034: RegVal = 1

--------------------

    1035: RegVal = 0

    1036: RegVal = 1

--------------------

    1037: RegVal = 0

    1038: RegVal = 1

--------------------

    1039: RegVal = 0

    1040: RegVal = 1

--------------------

    1041: RegVal = 0

    1042: RegVal = 1

--------------------

    1043: RegVal = 0

    1044: RegVal = 1

--------------------

    1045: RegVal = 0

    1046: RegVal = 1

--------------------

    1047: RegVal = 0

    1048: RegVal = 1

--------------------

    1049: RegVal = 0

    1050: RegVal = 1

--------------------

    1051: RegVal = 0

    1052: RegVal = 1

--------------------

    1053: RegVal = 0

    1054: RegVal = 1

--------------------

    1055: RegVal = 0

    1056: RegVal = 1

--------------------

    1057: RegVal = 0

    1058: RegVal = 1

--------------------

    1059: RegVal = 0

    1060: RegVal = 1

--------------------

    1061: RegVal = 0

    1062: RegVal = 1

--------------------

    1063: RegVal = 0

    1064: RegVal = 1

--------------------

    1065: RegVal = 0

    1066: RegVal = 1

--------------------

    1067: RegVal = 0

    1068: RegVal = 1

--------------------

    1069: RegVal = 0

    1070: RegVal = 1

--------------------

    1071: RegVal = 0

    1072: RegVal = 1

--------------------

    1073: RegVal = 0

    1074: RegVal = 1

--------------------

    1075: RegVal = 0

    1076: RegVal = 1

--------------------

    1077: RegVal = 0

    1078: RegVal = 1

--------------------

    1079: RegVal = 0

    1080: RegVal = 1

--------------------

    1081: RegVal = 0

    1082: RegVal = 1

--------------------

    1083: RegVal = 0

    1084: RegVal = 1

--------------------

    1085: RegVal = 0

    1086: RegVal = 1

--------------------

    1087: RegVal = 0

    1088: RegVal = 1

--------------------

    1089: RegVal = 0

    1090: RegVal = 1

--------------------

    1091: RegVal = 0

    1092: RegVal = 1

--------------------

    1093: RegVal = 0

    1094: RegVal = 1

--------------------

    1095: RegVal = 0

    1096: RegVal = 1

--------------------

    1097: RegVal = 0

    1098: RegVal = 1

--------------------

    1099: RegVal = 0

    1100: RegVal = 1

--------------------

    1101: RegVal = 0

    1102: RegVal = 1

--------------------

    1103: RegVal = 0

    1104: RegVal = 1

--------------------

    1105: RegVal = 0

    1106: RegVal = 1

--------------------

    1107: RegVal = 0

    1108: RegVal = 1

--------------------

    1109: RegVal = 0

    1110: RegVal = 1

--------------------

    1111: RegVal = 0

    1112: RegVal = 1

--------------------

    1113: RegVal = 0

    1114: RegVal = 1

--------------------

    1115: RegVal = 0

    1116: RegVal = 1

--------------------

    1117: RegVal = 0

    1118: RegVal = 1

--------------------

    1119: RegVal = 0

    1120: RegVal = 1

--------------------

    1121: RegVal = 0

    1122: RegVal = 1

--------------------

    1123: RegVal = 0

    1124: RegVal = 1

--------------------

    1125: RegVal = 0

    1126: RegVal = 1

--------------------

    1127: RegVal = 0

    1128: RegVal = 1

--------------------

    1129: RegVal = 0

    1130: RegVal = 1

--------------------

    1131: RegVal = 0

    1132: RegVal = 1

--------------------

    1133: RegVal = 0

    1134: RegVal = 1

--------------------

    1135: RegVal = 0

    1136: RegVal = 1

--------------------

    1137: RegVal = 0

    1138: RegVal = 1

--------------------

    1139: RegVal = 0

    1140: RegVal = 1

--------------------

    1141: RegVal = 0

    1142: RegVal = 1

--------------------

    1143: RegVal = 0

    1144: RegVal = 1

--------------------

    1145: RegVal = 0

    1146: RegVal = 1

--------------------

    1147: RegVal = 0

    1148: RegVal = 1

--------------------

    1149: RegVal = 0

    1150: RegVal = 1

--------------------

    1151: RegVal = 0

    1152: RegVal = 1

--------------------

    1153: RegVal = 0

    1154: RegVal = 1

--------------------

    1155: RegVal = 0

    1156: RegVal = 1

--------------------

    1157: RegVal = 0

    1158: RegVal = 1

--------------------

    1159: RegVal = 0

    1160: RegVal = 1

--------------------

    1161: RegVal = 0

    1162: RegVal = 1

--------------------

    1163: RegVal = 0

    1164: RegVal = 1

--------------------

    1165: RegVal = 0

    1166: RegVal = 1

--------------------

    1167: RegVal = 0

    1168: RegVal = 1

--------------------

    1169: RegVal = 0

    1170: RegVal = 1

--------------------

    1171: RegVal = 0

    1172: RegVal = 1

--------------------

    1173: RegVal = 0

    1174: RegVal = 1

--------------------

    1175: RegVal = 0

    1176: RegVal = 1

--------------------

    1177: RegVal = 0

    1178: RegVal = 1

--------------------

    1179: RegVal = 0

    1180: RegVal = 1

--------------------

    1181: RegVal = 0

    1182: RegVal = 1

--------------------

    1183: RegVal = 0

    1184: RegVal = 1

--------------------

    1185: RegVal = 0

    1186: RegVal = 1

--------------------

    1187: RegVal = 0

    1188: RegVal = 1

--------------------

    1189: RegVal = 0

    1190: RegVal = 1

--------------------

    1191: RegVal = 0

    1192: RegVal = 1

--------------------

    1193: RegVal = 0

    1194: RegVal = 1

--------------------

    1195: RegVal = 0

    1196: RegVal = 1

--------------------

    1197: RegVal = 0

    1198: RegVal = 1

--------------------

    1199: RegVal = 0

    1200: RegVal = 1

--------------------

    1201: RegVal = 0

    1202: RegVal = 1

--------------------

    1203: RegVal = 0

    1204: RegVal = 1

--------------------

    1205: RegVal = 0

    1206: RegVal = 1

--------------------

    1207: RegVal = 0

    1208: RegVal = 1

--------------------

    1209: RegVal = 0

    1210: RegVal = 1

--------------------

    1211: RegVal = 0

    1212: RegVal = 1

--------------------

    1213: RegVal = 0

    1214: RegVal = 1

--------------------

    1215: RegVal = 0

    1216: RegVal = 1

--------------------

    1217: RegVal = 0

    1218: RegVal = 1

--------------------

    1219: RegVal = 0

    1220: RegVal = 1

--------------------

    1221: RegVal = 0

    1222: RegVal = 1

--------------------

    1223: RegVal = 0

    1224: RegVal = 1

--------------------

    1225: RegVal = 0

    1226: RegVal = 1

--------------------

    1227: RegVal = 0

    1228: RegVal = 1

--------------------

    1229: RegVal = 0

    1230: RegVal = 1

--------------------

    1231: RegVal = 0

    1232: RegVal = 1

--------------------

    1233: RegVal = 0

    1234: RegVal = 1

--------------------

    1235: RegVal = 0

    1236: RegVal = 1

--------------------

    1237: RegVal = 0

    1238: RegVal = 1

--------------------

    1239: RegVal = 0

    1240: RegVal = 1

--------------------

    1241: RegVal = 0

    1242: RegVal = 1

--------------------

    1243: RegVal = 0

    1244: RegVal = 1

--------------------

    1245: RegVal = 0

    1246: RegVal = 1

--------------------

    1247: RegVal = 0

    1248: RegVal = 1

--------------------

    1249: RegVal = 0

    1250: RegVal = 1

--------------------

    1251: RegVal = 0

    1252: RegVal = 1

--------------------

    1253: RegVal = 0

    1254: RegVal = 1

--------------------

    1255: RegVal = 0

    1256: RegVal = 1

--------------------

    1257: RegVal = 0

    1258: RegVal = 1

--------------------

    1259: RegVal = 0

    1260: RegVal = 1

--------------------

    1261: RegVal = 0

    1262: RegVal = 1

--------------------

    1263: RegVal = 0

    1264: RegVal = 1

--------------------

    1265: RegVal = 0

    1266: RegVal = 1

--------------------

    1267: RegVal = 0

    1268: RegVal = 1

--------------------

    1269: RegVal = 0

    1270: RegVal = 1

--------------------

    1271: RegVal = 0

    1272: RegVal = 1

--------------------

    1273: RegVal = 0

    1274: RegVal = 1

--------------------

    1275: RegVal = 0

    1276: RegVal = 1

--------------------

    1277: RegVal = 0

    1278: RegVal = 1

--------------------

    1279: RegVal = 0

    1280: RegVal = 1

--------------------

    1281: RegVal = 0

    1282: RegVal = 1

--------------------

    1283: RegVal = 0

    1284: RegVal = 1

--------------------

    1285: RegVal = 0

    1286: RegVal = 1

--------------------

    1287: RegVal = 0

    1288: RegVal = 1

--------------------

    1289: RegVal = 0

    1290: RegVal = 1

--------------------

    1291: RegVal = 0

    1292: RegVal = 1

--------------------

    1293: RegVal = 0

    1294: RegVal = 1

--------------------

    1295: RegVal = 0

    1296: RegVal = 1

--------------------

    1297: RegVal = 0

    1298: RegVal = 1

--------------------

    1299: RegVal = 0

    1300: RegVal = 1

--------------------

    1301: RegVal = 0

    1302: RegVal = 1

--------------------

    1303: RegVal = 0

    1304: RegVal = 1

--------------------

    1305: RegVal = 0

    1306: RegVal = 1

--------------------

    1307: RegVal = 0

    1308: RegVal = 1

--------------------

    1309: RegVal = 0

    1310: RegVal = 1

--------------------

    1311: RegVal = 0

    1312: RegVal = 1

--------------------

    1313: RegVal = 0

    1314: RegVal = 1

--------------------

    1315: RegVal = 0

    1316: RegVal = 1

--------------------

    1317: RegVal = 0

    1318: RegVal = 1

--------------------

    1319: RegVal = 0

    1320: RegVal = 1

--------------------

    1321: RegVal = 0

    1322: RegVal = 1

--------------------

    1323: RegVal = 0

    1324: RegVal = 1

--------------------

    1325: RegVal = 0

    1326: RegVal = 1

--------------------

    1327: RegVal = 0

    1328: RegVal = 1

--------------------

    1329: RegVal = 0

    1330: RegVal = 1

--------------------

    1331: RegVal = 0

    1332: RegVal = 1

--------------------

    1333: RegVal = 0

    1334: RegVal = 1

--------------------

    1335: RegVal = 0

    1336: RegVal = 1

--------------------

    1337: RegVal = 0

    1338: RegVal = 1

--------------------

    1339: RegVal = 0

    1340: RegVal = 1

--------------------

    1341: RegVal = 0

    1342: RegVal = 1

--------------------

    1343: RegVal = 0

    1344: RegVal = 1

--------------------

    1345: RegVal = 0

    1346: RegVal = 1

--------------------

    1347: RegVal = 0

    1348: RegVal = 1

--------------------

    1349: RegVal = 0

    1350: RegVal = 1

--------------------

    1351: RegVal = 0

    1352: RegVal = 1

--------------------

    1353: RegVal = 0

    1354: RegVal = 1

--------------------

    1355: RegVal = 0

    1356: RegVal = 1

--------------------

    1357: RegVal = 0

    1358: RegVal = 1

--------------------

    1359: RegVal = 0

    1360: RegVal = 1

--------------------

    1361: RegVal = 0

    1362: RegVal = 1

--------------------

    1363: RegVal = 0

    1364: RegVal = 1

--------------------

    1365: RegVal = 0

    1366: RegVal = 1

--------------------

    1367: RegVal = 0

    1368: RegVal = 1

--------------------

    1369: RegVal = 0

    1370: RegVal = 1

--------------------

    1371: RegVal = 0

    1372: RegVal = 1

--------------------

    1373: RegVal = 0

    1374: RegVal = 1

--------------------

    1375: RegVal = 0

    1376: RegVal = 1

--------------------

    1377: RegVal = 0

    1378: RegVal = 1

--------------------

    1379: RegVal = 0

    1380: RegVal = 1

--------------------

    1381: RegVal = 0

    1382: RegVal = 1

--------------------

    1383: RegVal = 0

    1384: RegVal = 1

--------------------

    1385: RegVal = 0

    1386: RegVal = 1

--------------------

    1387: RegVal = 0

    1388: RegVal = 1

--------------------

    1389: RegVal = 0

    1390: RegVal = 1

--------------------

    1391: RegVal = 0

    1392: RegVal = 1

--------------------

    1393: RegVal = 0

    1394: RegVal = 1

--------------------

    1395: RegVal = 0

    1396: RegVal = 1

--------------------

    1397: RegVal = 0

    1398: RegVal = 1

--------------------

    1399: RegVal = 0

    1400: RegVal = 1

--------------------

    1401: RegVal = 0

    1402: RegVal = 1

--------------------

    1403: RegVal = 0

    1404: RegVal = 1

--------------------

    1405: RegVal = 0

    1406: RegVal = 1

--------------------

    1407: RegVal = 0

    1408: RegVal = 1

--------------------

    1409: RegVal = 0

    1410: RegVal = 1

--------------------

    1411: RegVal = 0

    1412: RegVal = 1

--------------------

    1413: RegVal = 0

    1414: RegVal = 1

--------------------

    1415: RegVal = 0

    1416: RegVal = 1

--------------------

[0;32mI (29295) uart_example: ring buffer full
[0m
[0;32mI (29405) uart_example: hw fifo overflow
[0m
[0;32mI (29535) uart_example: hw fifo overflow
[0m

: log_saved.png (29.78 KiB) Viewed 28817 times

rudi ;-) · Postby **rudi ;-)** » Fri Nov 25, 2016 3:42 am

two ESP32 plays now CAN Ping Pong with a counter
few things ( few register entries ) must be done but :

99,999 prozent stable now

(controll monitoring)

: ESP32_CAN_TRANSEIVER_CONTROLLER_BASE_REGISTER_DONE.png (113.24 KiB) Viewed 28755 times

(logic)

: loc_esp32_can.png (71.87 KiB) Viewed 28755 times

best wishes
rudi

uhrheber · Postby **uhrheber** » Fri Nov 25, 2016 7:11 am

Great!
What can transceivers did you use?

eerimoq · Postby **eerimoq** » Sat Nov 26, 2016 7:46 am

Hi,

I pushed the SimbaOS implementation of the CAN driver to GitHub. It can successfully transmit and receive CAN frames to/from an ARM MCU (SAM3X8E) on the same CAN bus.

Here is the commit that adds ESP32 CAN support:
https://github.com/eerimoq/simba/commit ... 3916cfaa06

Error handling shall be implemented to finalize the driver. Not planned atm.

Feel free to create an IDF component based on this implementation. It's MIT licensed so no restrictions.

Postby **ESP_Sprite** » Sun Nov 27, 2016 1:47 am

Nice! Thank you very much. I'll see if we can integrate it into esp-idf.

About the CAN controller.

Re: About the CAN controller.

Re: About the CAN controller.

Re: About the CAN controller.

Re: About the CAN controller.

Re: About the CAN controller.

Re: About the CAN controller.

Re: About the CAN controller.

Re: About the CAN controller.

Re: About the CAN controller.

Re: About the CAN controller.

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