I2S-parallel example: Drive a 64x32 display

[rudi ;-)]

- The frame display mechanism has a few issues - the left most (zero) pixel seems to be wrapped from the right hand side of the display (should be easy to fix) and there are some ghosting issues especially with green (not sure where this is coming from)
Certainly needs some work but shows the capabilities of the chip and a cheap display.

interesting
with JINX! with "Simple color" and Main Mix "Move left right"

must_be.png (13.96 KiB) Viewed 47654 times

the found can be pretty watch what you describe
( protokol on right side )

IMG_9422_S.jpg (192.53 KiB) Viewed 47654 times

btw
a short test with my frame test and with tmp2.net protokol is the same.
i use your tmp2.net server version with this for a test.
the pixel(0,0) comes on frame(1,0) and light on frame(1,15)

IMG_9420_S.jpg (56.87 KiB) Viewed 47654 times

the cat animation runs pretty well with jeroen version, so i think, there is a (bit) custom work need in this server version.
perhabs an index mistake 0, 1

btw, i work with pascal ( Delphi )
Pixel(0,0) FF FF FF

Code: Select all

procedure TForm1.SetLedClick(Sender: TObject);
 var
   testframe : array[1..10] of byte;
  begin
   testframe[1] := $9C; // start byte 9C
   testframe[2] := $DA; // type DATA..
   testframe[3] := $00; // high byte leng of data
   testframe[4] := $03; // low byte leng of data
   testframe[5] := $01; // paketnummer
   testframe[6] := $01; // pakete total
   testframe[7] := $FF; // data R
   testframe[8] := $FF; // data G
   testframe[9] := $FF; // dara B
   testframe[10]:= $36; // endpacket
   IdUDPClient1.Port := 65506;
   IdUDPClient1.Host := '192.168.4.1' ;
   IdUDPClient1.Active := true;
   IdUDPClient1.SendBuffer(testframe,10);
   IdUDPClient1.Active := false;
 end;

clear it
pixel(0,0) 00 00 00

Code: Select all

procedure TForm1.CLSLedClick(Sender: TObject);
 var
   testframe : array[1..10] of byte;
  begin
   testframe[1] := $9C; // start byte 9C
   testframe[2] := $DA; // type DATA..
   testframe[3] := $00; // high byte leng of data
   testframe[4] := $03; // low byte leng of data
   testframe[5] := $01; // paketnummer
   testframe[6] := $01; // pakete total
   testframe[7] := $00; // data R
   testframe[8] := $00; // data G
   testframe[9] := $00; // dara B
   testframe[10]:= $36; // endpacket
   IdUDPClient1.Port := 65506;
   IdUDPClient1.Host := '192.168.4.1' ;
   IdUDPClient1.Active := true;
   IdUDPClient1.SendBuffer(testframe,10);
   IdUDPClient1.Active := false;
 end;

best wishes
rudi

[rudi ;-)]

*info
i use this 64x32 p3 panel
P3-(2121)64*32-16S-D1.0

left side: 0,124 A ( 124mA ) save/sleep mode is R=00 G=00 B=00

right side: 2,601 (2601mA) full mode is R=FF G=FF B=FF

Power_64x32_P3-2121-16SD1.0.jpg (177.88 KiB) Viewed 47631 times

best wishes
rudi

[rudi ;-)]

@wobblyboots
txs again. few hours after, i figured (indexing) it out now. all data fly to the right pixel, line, row, column

64x32_ok_now.jpg (135.86 KiB) Viewed 47577 times

@jeroen
txs again

keep this in mind - this is a great example for I2S, shift, latches, and in RTOS for semaphore.( update, give and more )
i try to make few changes now for an expand ( more clients, more panels.. )

best wishes
rudi

[Olof Astrand]

Hello Friends,
Really interesting application and example.
I just ordered a similar display from China.
It seems that you drive the display directly from the ESP32.
What Vcc-voltage for the display are you using 3.6V or 5.0V?
/Olof

[rudi ;-)]

Hello Friends,
Really interesting application and example.
I just ordered a similar display from China.
It seems that you drive the display directly from the ESP32.
What Vcc-voltage for the display are you using 3.6V or 5.0V?
/Olof

hi Olof,

here at this display it is 5V for VCC and GND



ESP32 drive the Panel, there are ICN2012, ICN2028A and SM245TS chips on the 64x32 RGB Frame

I use a 5V 3A power supply for this, cause my test



was with full white led's near 2,6 A, so i think it is enough for one panel.

hope this helps.

best wishes
rudi

[Olof Astrand]

Thanks @rudi

I will get a 5V 4A supply.

I ordered this LED panel

https://www.aliexpress.com/item/P4-Indo ... 0.0.c1pPY2

I also ordered this SALEAE clone
https://www.aliexpress.com/item/New-USB ... 0.0.c1pPY2

I will keep you posted of my progress.
Keep up your great work.

/Olof

[rudi ;-)]

Happy Santa Claus

think this is great x-mas project
so code is on Github now
- Base version
- NetworkVersion

and last but not least
here is the first OSH project for this by BirdTechstep

64x32_ESP32_HUB75-WIFI-Adapter_Bird_Techstep.png (132.55 KiB) Viewed 47477 times

@wobblyboots
i took back the 63 to 62 for the left most (zero) pixel


best wishes
rudi

[boilerbots]

Thanks for the code this is really great. I have a 64x32 display and put up code on GitHub last August that was a proof of concept just bit-banging and was able to refresh the display with a single dedicated core at about 10KHz. I just sat down to attempt using the I2S DMA mode, was always on my mind, when I happened to find this thread. I redefined the pins to match my layout and it works great.

The panel that I use, purchased through ebay works great, I moved the LATCH back to 63 and my display is perfect without any column shift. I run my at 10MHz clock speed with the display at 3.7V since the inputs are just TTL and it works as a quick hack.

I would put level shifters on a board if I where to lay out one. I think one of these panels would make a great high brightness wall clock with the wifi used for syncing with NTP.

[Vader_Mester]

My question is related to the parallel I2S driver in general.

How does the WS signal work in I2S parallel mode?
For example if I configure the bus to be 8bit wide, but the word length is 16bits, then the two half of the 16bit word will be clocked out with BCK, and WS will be 2BCK cycles long, with the high part (1BCK cycle) of the WS cycle signaling the 1st half and low part (1BCK cylce) for the 2nd, if I'm correct. (I know WS can be inverted).

By the way the above is what I want to achieve with the I2S, and reading the technical ref I'm pretty much confused on how BCK and WS are related in parallel and how flexible I2S is.

Generally I just want to achive a general half-duplex 8bit with parallel bus, with 16bit words, where 1 WS cycle is the length of some even number of BCK cycles (like 1WS can be 2, 4 8, etc BCK cycles long)... whichever is easier to set up.

It would be nice if someone gives some insight on how it works, cause you are the ones who know more about the I2S parrallel driver than anyone else.

Thanks in advance!

[rudi ;-)]

hi

have a note and look to the video on Thongchai Artsamart‏ @BirdTehstep channel
there is now work on more ESP32 and more panels too.
this can help for separate to group of panels for building big screen

best wishes
rudi