help with bundles for GPIO

[MicroController]

in both output input mode, setting the output high, reading the input is kind of pointless because it will also be high same as low.

Correct. That's why you may want to use open drain mode.

For a better understanding, I suggest you look at the GPIO matrix and IOMUX in the TRM. It shows which settings/bits affect a pin at which level.

but then how to clear bits, I can only write a bit.

As I said: Tri-stating a pin means disabling its output, which is done via bits in the IOMUX's registers, not via the dedicated GPIO port of the CPU.

If the input and output can co-exist then we need two registers for that, not one

Not really. There is no requirement for a register to read the same value which was written to it.
For example, in the ESPs there are a few hardware FIFO buffers, each accessed via a single register so that a write enqueues data to be sent while a read retrieves data previously received.

[ulaoulao]

" I suggest you look at the GPIO matrix and IOMUX in the TRM" -- where is that?

I saw this
https://espressif-docs.readthedocs-host ... o_mux.html
but its not much.

[MicroController]

Technical Reference Manual, chapter 6 "IO MUX and GPIO Matrix"

[ulaoulao]

was very helpful

I think there maybe a bug here.

using
const int bundleA_gpios[] = {0,1,2,3};

allows pins 1,2 and 3 to swtich. Also as a side note ( see below ) only pin 3 is fast.

using
const int bundleA_gpios[] = { 1,2,3};

I can not use pin 3, its like the array has to start at 0




about the comment about speed

use test code like this
#define DEBUG __asm__ __volatile__ ("ee.set_bit_gpio_out %0\n nop\n nop \n ee.clr_bit_gpio_out %0" : : "I"(DEBUG_BIT) : );
while(1){DEBUG};
with pin 3 I get 24 ss gaps
with pin 1 and 2 I get 9ms



also why does (dedic_gpio_del_bundle(&bundleA)); give me E (336) dedic_gpio: dedic_gpio_del_bundle(318): del bundle on wrong CPU


and this is only asking for problems, what is this?

esp_err_t dedic_gpio_del_bundle(dedic_gpio_bundle_handle_t bundle)
{
esp_err_t ret = ESP_OK;
bool recycle_all = false;
ESP_GOTO_ON_FALSE(bundle, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");

uint32_t core_id = esp_cpu_get_core_id();
.
.

esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_gpio_bundle_handle_t *ret_bundle)
{
esp_err_t ret = ESP_OK;
dedic_gpio_bundle_t *bundle = NULL;
uint32_t out_mask = 0;
uint32_t in_mask = 0;
int core_id = esp_cpu_get_core_id(); // dedicated GPIO will be binded to the CPU who invokes this API
.
.
.

and
struct dedic_gpio_bundle_t {
int core_id;
.
.
.

if I make them al ints it tries to compere
core_id: 1 to 1070156032

not t mention many other places in this file

lets at least keep the cast the same.

[MicroController]

Yeah, I think it's not really well documented, or at all:
On the S3, each CPU core has its own 8 bits of dedicated GPIO. The good news is that this allows for up to 16 pins to be 'fast'. The bad news is that code/a task currently running on one core cannot access the fast GPIO allocated on/routed to the other core.
Easiest work-around might be to do all dedicated GPIO stuff from a single task explicitly pinned to one core.

[ulaoulao]

yeah that's fine but I do not see how I'm not doing this.

all of my code is ran from core 1

xTaskCreatePinnedToCore (Start_LLAPI, "none", 4096, (void *)1, 1, NULL, 1);

all of my bundles are < 8

What did I do wrong that violated this?