[Answered] Assembler language reference manual ...

[kolban]

Do we have access to an assembler language reference manual for the processor that runs the ESP32?

The back story is that I want to drive the low level timings of NeoPixels/WS2812s from an ESP32. We were able to achieve this on the ESP8266 using an assembly language construct that looked as follows:

Code: Select all

static inline uint32_t _getCycleCount(void) {
  uint32_t ccount;
  __asm__ __volatile__("rsr %0,ccount":"=a" (ccount));
  return ccount;
}

When called, this would return the number of CPU cycles between calls. Knowing the clock frequency, we could then busy block for until some number of cycles had elapsed. This gave us the opportunity to delay/block at the 10's of nanosecond range needed for good quality WS2812 signals.

Now I haven't tried the above code fragment (which is good for ESP8266) on the ESP32 but rather than cross my fingers and hope it works, I'd like to know for sure ... and hence the question about the assembly language reference.

[ESP_Sprite]

Specific to what you want to do (WS8211): Don't. We have the RMT (Remote Control) peripheral, which, contrary to its name, can be abused to generate random signals pretty easily. It's partially developed to make controlling WS8211s easy. Please check the techdoc and the example in esp-idf on how to use it.

In general: The Xtensa docs on the core we use are pretty good. The problem with it is that, as far as I know, we have them because we signed an NDA with Cadence, making it hard to just spread them around. We know this is an issue, and we're working on getting the info out one way or another. People did awesome things using assembly on the ESP8266; we want to see awesome things with the ESP32 as well, so we have to spread this information one way or another.

[WiFive]

In fact, don't even do it on esp8266, use the i2s driver: https://github.com/cnlohr/esp8266ws2812i2s

[jmattsson]

Not quite what you asked for, but you can find the overall Xtensa Instruction Set Architecture (ISA) Reference Manual document e.g. here. It's not specific to the 108s that you'll find in the ESP32, but between the ISA doc and the components/esp32/include/xtensa/config/core-isa.h header you can pretty much work out what applies.

[ESP_igrr]

Not quite what you asked for, but you can find the overall Xtensa Instruction Set Architecture (ISA) Reference Manual document e.g. here. It's not specific to the 108s that you'll find in the ESP32, but between the ISA doc and the components/esp32/include/xtensa/config/core-isa.h header you can pretty much work out what applies.

Please note that this is a pretty old version of ISA RM. It's not easy to diff PDFs so i can't say what exactly has changed, but a brief look shows that at least FPU documentation in that version doesn't match the latest one.

As Sprite has mentioned above, we will release up-to-date documentation once we get permission from Cadence.

[hydrabus]

Not quite what you asked for, but you can find the overall Xtensa Instruction Set Architecture (ISA) Reference Manual document e.g. here. It's not specific to the 108s that you'll find in the ESP32, but between the ISA doc and the components/esp32/include/xtensa/config/core-isa.h header you can pretty much work out what applies.

Please note that this is a pretty old version of ISA RM. It's not easy to diff PDFs so i can't say what exactly has changed, but a brief look shows that at least FPU documentation in that version doesn't match the latest one.

As Sprite has mentioned above, we will release up-to-date documentation once we get permission from Cadence.

Do you have any news about that as it is very important to have information on instruction set supported by ESP32 (and the extensions available and also number of cycle required for each instruction ...) ?

[ESP_Sprite]

Not yet, sorry; we've requested it at Cadence, but they still have to get back to us. Be assured we post what we can as soon as we have their permission.

You seem to need this manual ASAP. Can I ask what you want to make with it? Maybe there's a different way of solving your problem.

[ESP_igrr]

As for the number of cycles required for each instruction: please note that this information is not in the Instruction Set Architecture reference manual, because this behaviour is implementation-dependent.
You can find an older version of the document on the Internet, just google for "xtensa isa_rm.pdf". Latest version has differences in FPU registers/instructions. If you need that for your application, please contact Espressif directly and we will get you the necessary information.

[hydrabus]

Not yet, sorry; we've requested it at Cadence, but they still have to get back to us. Be assured we post what we can as soon as we have their permission.

You seem to need this manual ASAP. Can I ask what you want to make with it? Maybe there's a different way of solving your problem.

My requirements are mainly for hard real-time processing (even if 99% is coded in portable C code):

1) A way to Count Leading Zeros of a 32bits unsigned integer (for example on ARM CM3/4 I'm using #define CountLeadingZero(x) (__CLZ(x))) for my needs it is not possible to use equivalent C code as it takes too much cycles ... so it is mandatory to have a 1 cycle instruction for that.
Does such feature exist on ESP32 CPU ?

2) In a near future write an IDA Pro Processor Module for ESP32 (as only ESP8266 is supported ...)

Not really related to assembly language:
3) Documentation/Example how to use Download Mode SDIO_REI_REO_V2 (does there is special header things vs UART download ?)
- Does it work using simple SPI, DualSPI or QuadSPI ? (and how to select that ?)

4) A way to retrieve number of cycles executed (with accuracy of CPU clock so 240MHz) on 64bits if possible (but I can survive with 32bits), CPU cycle counter (like on ARM CM3... => DWTBase->CYCCNT) is perfect for that (even if timer can be also used ...)

5) A way (API) to configure SPI as slave using DMA with double buffer(ping pong buffer configured in a circular way) and of course a way to know what is the buffer in use/work in progress by SPI/DMA

6) An API to configure SPI as Master and Receive/Send data over SPI (with DMA if possible without IRQ enabled, I would prefer to use official esp-idf API than re-inventing the wheel ...)

7) An API to configure UART (or HighSpeed UART...) and Receive/Send data over UART (with DMA if possible without IRQ enabled, I would prefer to use official esp-idf API than re-inventing the wheel ...)

[ESP_igrr]

1) A way to Count Leading Zeros of a 32bits unsigned integer
Does such feature exist on ESP32 CPU ?

Yes, using NSAU instruction. Compiler will generate it if you use GCC __builtin_clz() intrinsic.

2) In a near future write an IDA Pro Processor Module for ESP32 (as only ESP8266 is supported ...)

I have extended the 8266 ida-python plugin with some of the ESP32 instructions (not added FP yet) and am using it personally in day-to-day debugging using ScratchABit disassembler. I can share what i have if you want to work on this.

4) A way to retrieve number of cycles executed (with accuracy of CPU clock so 240MHz) on 64bits if possible (but I can survive with 32bits), CPU cycle counter (like on ARM CM3... => DWTBase->CYCCNT) is perfect for that (even if timer can be also used ...)

32-bit CPU cycle counter can be queried by reading CCOUNT special register, or equivalently, using xthal_get_ccount function defined in Xtensa HAL.