LP Core on ESP32-C6

[**txf**]

I'm somewhat confused about this core, how is it different from the ULP-RiscV core on previous devices?

I noticed in the documentation that it has an interrupt controller, Does this mean it also supports GPIO interrupts? If so, is there any API to use interrupts, I can only see basic GPIO features, will the functions in "hal\rtc_io_ll.h" work?

[JoeSensoric]

I think the C6 LP CORE is different to the ULP-RISC-V CPU used in S2 and S3. The API is different and also the implemented RISC-V-Features. I asked some questions about the C6 LP CORE last week: viewtopic.php?f=13&t=37705

I think the API is still under progress.