ESP32 UART FIFO Operation

[berlinetta]

Hello Microcontroller,

I have been monitoring the UART0 registers while single-stepping through the code, particularly the STATUS register (watching the "UART_RX_FIFO_CNT" parameter) and the MEM_RX_STATUS register (watching the "rd_addr" parameter). What I noticed was quite interesting...

Each time I transmit a character on UART0, the UART_RX_FIFO_CNT decreases by '1' and the rd_addr of the MEM_RX_STATUS register increases by '1'.

The combination of this characterization of operation coupled with previous testing which proved my UART handler was solely in control of the UART interrupt management appears to exonerate any other code from popping characters off the UART0 receive FIFO.

Again, this only happens on ESP-IDF releases of v4.4.x and newer. The same code does not cause this anomaly.

Does anyone have any explanation as to why this is occurring? The simple operation of writing a character to the UART0 FIFO register (0x3FF40000) should not be affecting the receive FIFO rd_addr or UART_RX_FIFO_CNT parameters.

Best Regards,
Mark

[berlinetta]

Hello MicroController,

I have finally resolved this issue by changing all FIFO write attempts to utilize the WRITE_PERI_REG macro. If this macro is not used, I am presuming something in the system cache operation must be performing look-ahead reads of the FIFO register, causing the change in rd_addr and UART_RX_FIFO_CNT parameters.

What I cannot figure out is why this is only pertinent to ESP-IDF releases of v4.4.x and greater.

Best Regards,
Mark

[MicroController]

Glad you got it working