I went looking for an example of using the QuadSPI on the ESP32S2 in slave mode and couldn't find one. So I wrote one and am sharing it case anyone in the future goes down this road:
https://gitlab.com/kevinwolfe/esp32s2_qspi
All source code is in a single file: ./main/main.c
Test script included: ./tools/test_qspi.py (requires 'ft4222' lib, "pip install ft4222").
I am using an FT4222 development board in master to interact with the device. It's not a perfect example. First, I'm only doing DMA operations. Next, I could not get QuadSPI reads to work (e.g. master/host PC reads data from ESP32S2 slave device). Writes worked fine. My work-around is to only ever use QPI mode, which firmware automatically enters during SPI init. And lastly, I could only get QPI reads to work if I set the dummy bytes to 0xFF. No idea why that's the case, but it is what it is.
Good luck.
ESP32S2 - Quad SPI Slave / QPI Example + Notes
Re: ESP32S2 - Quad SPI Slave / QPI Example + Notes
Hello KWolfe81,
I would like to use Quad SPI in slave mode on my ESP32 S3. I'm interesting by your example. But your link is down, can you reload it ?
Thanks
I would like to use Quad SPI in slave mode on my ESP32 S3. I'm interesting by your example. But your link is down, can you reload it ?
Thanks
Re: ESP32S2 - Quad SPI Slave / QPI Example + Notes
Hello KWolfe81, Me too Please.
Re: How to use the upper 4MB of ESP-Wrover 8MB PSRAM
Hello,
I am using an ESP-Wrover-Kit.
It has a 16MB external SPI flash and an additional 8 MB PSRAM.
In the datasheet, it is mentioned that up to 4 MB of PSRAM can be mapped into CPU data memory space at a time.
As only 4 MB memory space is considered for External SRAM (0x3F80_0000 to 0x3FBF_FFFF), how can I use (map) the extra 4MB?
What would be the CPU data memory address to map that extra 4MB?
Is there an option to use part of the 4MB mappable addres srange to bank-switch the remaining memory in?
Do any one have a clue and similar situation for me to take a reference?
Thanks!
I am using an ESP-Wrover-Kit.
It has a 16MB external SPI flash and an additional 8 MB PSRAM.
In the datasheet, it is mentioned that up to 4 MB of PSRAM can be mapped into CPU data memory space at a time.
As only 4 MB memory space is considered for External SRAM (0x3F80_0000 to 0x3FBF_FFFF), how can I use (map) the extra 4MB?
What would be the CPU data memory address to map that extra 4MB?
Is there an option to use part of the 4MB mappable addres srange to bank-switch the remaining memory in?
Do any one have a clue and similar situation for me to take a reference?
Thanks!
Who is online
Users browsing this forum: Corand and 129 guests