Watchdog Reset By handle_livelock_int

[thethinker]

Hello,
We have built a product using ESP32-PICO-V3-MINI module. We do use the 2MB PSRAM mostly for a large queue and also Task stacks. We get lots of watch dog resets related to live lock(Using IDF V5.1 stable release):
0x40081c84: .handle_livelock_int at C:/Espressif/frameworks/esp-idf-v5.1/components/esp_system/port/soc/esp32/highint_hdl.S:398

I'm assuming this is the one mentioned in section 3.15 of the errata:
https://www.espressif.com/sites/default ... ata_en.pdf

By making sure WiFi and LWIP memories are not placed in PSRAM we managed to reduce the number of Watchdog resets, now it about once every two hours, however it still happens. Based on the Errata it seems like there is a work around already implemented for this, however it seems like it's not working in my case.
Any help or pointers as to how I can address this issue would be appriciated.

[ESP_Sprite]

What you're looking at _is_ the workaround. Can you give a full backtrace of the program when this happens? Are you doing anything with watchdogs yourself?

[thethinker]

Hello,
interesting thing is when this happens I get no trace of any shape since CPU locks up, it just reboots and on the next boot it prints the PC mentioned above. Is there any other method to get more info from it to send you?

[ESP_Sprite]

Can you post the entire log of such an event?

Looking at the code, it actually looks like it's waiting for core 1 to also enter the livelock code: core 1 doesn't seem to do this for whatever reason and core 0 keeps waiting until the stage of the watchdog where it resets the CPU triggers. Anything in particular you're doing on core 1?

[thethinker]

Hello,
Is it possible to send this privately in chat or email? the entire log has company sensitive information.

Both cores run freertos, core 1 has some of the tasks pinned to it including LWIP.

[ESP_Sprite]

Sure, feel free to send it to jeroen at espressif dot com.