The ROM bootloader prints a couple lines on boot:
Build:Mar 27 2021
rst:0x1 (POWERON),boot:0x2b (SPI_FAST_FLASH_BOOT)
I'm debugging a boot problem where the output of the boot:0x0x[0-9a-fA-F]* changes between 0x0 and 0x23. The accompanying text for both is identical: (DOWNLOAD(USB/UART0)). What is the difference in meaning between these two enumerations?
This post viewtopic.php?f=2&t=27495&p=96285&hilit ... ing#p96285 says that 0x0 indicates that all strapping pins are pulled low. Is this correct? If so, under what conditions would a voltage measurement indicate that strapping pins are pulled high, yet the ROM bootloader reads them as being pulled low?
Below is a list of boot:0x[0-9a-fA-F]* enums which appear in ESP-IDF documentation:
boot:0x0 (DOWNLOAD(USB/UART0))
boot:0x2 (DOWNLOAD_BOOT(UART0/UART1/SDIO_REI_FEO_V2))
boot:0x6 (DOWNLOAD_BOOT(UART0/UART1/SDIO_REI_FEO_V2))
boot:0x8 (SPI_FAST_FLASH_BOOT)
boot:0xc (SPI_FAST_FLASH_BOOT)
boot:0xf (SPI_FAST_FLASH_BOOT)
boot:0x13 (SPI_FAST_FLASH_BOOT)
boot:0x18 (SPI_FAST_FLASH_BOOT)
boot:0x1e (SPI_FAST_FLASH_BOOT)
boot:0x23 (DOWNLOAD(USB/UART0))
boot:0x2b (SPI_FAST_FLASH_BOOT)
boot:0x2f (UART_BOOT (UART0))
boot:0x33 (SPI_FAST_FLASH_BOOT)
What is the meaning of boot:0xNN in the ROM Bootloader UART output?
Re: What is the meaning of boot:0xNN in the ROM Bootloader UART output?
Thanks cruvus. That's just what I was looking for.
I've correlated the problem with me not properly implementing "2.2.1 Poweron Sequence" from the hardware design guidelines.
https://www.espressif.com/sites/default ... nes_en.pdf
CHIP_PU must rise only after 3.3V is up.
I've correlated the problem with me not properly implementing "2.2.1 Poweron Sequence" from the hardware design guidelines.
https://www.espressif.com/sites/default ... nes_en.pdf
CHIP_PU must rise only after 3.3V is up.
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