ESP32-S3 LCD and I2S FULL documentation

[ESP_Sprite]

Hi @ESP_Sprite,

What alignment setting for transfer in gdma should I use in psram ?

MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA should work

Another thing, I must use the function

Code: Select all

Cache_WriteBack_Addr( (uint32_t)p_buffer_a, length );

or the function

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esp_cache_msync( (void*)p_buffer_a, length, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_UNALIGNED );

Ideally esp_cache_msync, that is a 'more official' way to handle this; iirc Cache_WriteBack_Addr works as well but is a ROM function that may change in other ESP32 chips.

[Baldhead]

Hi @ESP_Sprite,

What alignment setting for transfer in gdma should I use in psram ?

MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA should work

Another thing, I must use the function

Code: Select all

Cache_WriteBack_Addr( (uint32_t)p_buffer_a, length );

or the function

Code: Select all

esp_cache_msync( (void*)p_buffer_a, length, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_UNALIGNED );

Ideally esp_cache_msync, that is a 'more official' way to handle this; iirc Cache_WriteBack_Addr works as well but is a ROM function that may change in other ESP32 chips.

Alignment i mean the address of returning memory from heap_caps_aligned_alloc(), ie, first parameter of this function.

It need to be 1, 2, 4 .... to gdma(edma) access external psram memory ?

[ESP_Sprite]

Alignment i mean the address of returning memory from heap_caps_aligned_alloc(), ie, first parameter of this function.

It need to be 1, 2, 4 .... to gdma(edma) access external psram memory ?

Ah, I didn't see you were using that. You don't need to; in recent ESP-IDF versions heap_caps_malloc and friends will already align to the correct size if you pass it MALLOC_CAPS_SPIRAM|MALLOC_CAPS_DMA. (I think heap_caps_aligned_alloc also does that so your code should be working anyway.)