请教一下ESP32C3-spi-AT的通讯详细逻辑

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xwb1899
Posts: 7
Joined: Mon Mar 13, 2023 10:10 am

请教一下ESP32C3-spi-AT的通讯详细逻辑

Postby xwb1899 » Mon Mar 13, 2023 10:23 am

目前在将ESP32C3的SPI-AT主机代码从ESP平台移植到STM32F4上,但是一直通讯失败,想请教一下各位ESP32C3工作在SPI-AT是的详细通讯逻辑,以及主机时序要求

yake827
Posts: 43
Joined: Mon Aug 09, 2021 7:51 am

Re: 请教一下ESP32C3-spi-AT的通讯详细逻辑

Postby yake827 » Wed Mar 15, 2023 2:36 am

有如下文档可以参考:
1. 介绍 SPI AT 的整理流程和原理: https://docs.espressif.com/projects/esp ... PI_AT.html
2. 以 AT\r\n 命令为例,详细说明了各个阶段的波形,还提供了逻辑分析仪的波形给你参考,请确保 STM32也是按照这个流程走的https://github.com/espressif/esp-at/tree/master/examples/at_spi_master/spi/esp32_c_series#communication-sample

xwb1899
Posts: 7
Joined: Mon Mar 13, 2023 10:10 am

Re: 请教一下ESP32C3-spi-AT的通讯详细逻辑

Postby xwb1899 » Wed Mar 15, 2023 12:10 pm

inline void spi_device_default_config(spi_device_interface_config_t* dev_cfg)
{
dev_cfg->clock_speed_hz = SPI_MASTER_FREQ_20M;
dev_cfg->mode = 0;
dev_cfg->spics_io_num = GPIO_CS;
dev_cfg->cs_ena_pretrans = 8;
dev_cfg->cs_ena_posttrans = 8;
dev_cfg->command_bits = 8;
dev_cfg->address_bits = 8;
dev_cfg->dummy_bits = 8;
dev_cfg->queue_size = 16;
dev_cfg->flags = SPI_DEVICE_HALFDUPLEX;
dev_cfg->input_delay_ns = 25;
}
您好,我是第一次接触ESP32C3芯片,我想请问一下主机端程序中,这个初始化设置最后一个参数input_delay_ns = 25;的用意在于什么

yake827
Posts: 43
Joined: Mon Aug 09, 2021 7:51 am

Re: 请教一下ESP32C3-spi-AT的通讯详细逻辑

Postby yake827 » Mon Apr 17, 2023 3:29 am

在注释中有对这个配置的说明,这个配置项只是时序上的一些改善,即使不使用也没有关系的。而且在你们移植的时候也不需要的,只是不同的芯片有一些特性,
int input_delay_ns; /**< Maximum data valid time of slave. The time required between SCLK and MISO
valid, including the possible clock delay from slave to master. The driver uses this value to give an extra
delay before the MISO is ready on the line. Leave at 0 unless you know you need a delay. For better timing
performance at high frequency (over 8MHz), it's suggest to have the right value.
*/

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