ESP32 Forum

Since the ESP-32 goes to baseband I/Q from 2.4 GHz to process WiFi and Bluetooth as a SDR, it strikes me that one of the DSP coprocessors advertised for the Tensilica Xtensa configurable processor intellectual property must be on the chip. It would be nice to be able to access the DSP. I am porting the Codec2 software and the chance of accelerating the FFT is interesting, among other things. I understand that getting Cadence to allow you to disclose this might be difficult.

Sorry, it is not. To my knowledge, the WiFi MAC is digital, but not a DSP; it's not reconfigurable. The Xtensa-core we have does have some DSP-ish instructions, most notably an 16-bit fixed-point multiply-accumulate instruction, but I'm not sure if that is documented anywhere in public documentation.

If it helps, chances are our next chip will have some extra instructions that can be used for accelerated FFT and given our plans won't change in the interim, we will probably have public sample code for this.

Bruce,

Just to see how it does, I thought I'd get the non-arm version of from Codec2-Ardino
https://github.com/blanu/codec2-arduino
working on esp32-arduino

Do you know how fast that fft needs to run in real-time?

I've been benchmarking
https://github.com/kosme/arduinoFFT


thanks

Hello,

I'm curious if anyone successfully completed the port?