ESP32 Forum

I'm interested in determining the feasibility of someday using the Rust programming language with the ESP32.

Currently, I know it's not possible, but I'd like to get some discussion started here to see what it would take.

I know there is very minimal support for Xtensa architecture within LLVM at the moment and having an LLVM backend would be a necessary prerequisite for supporting Rust as well as many other languages built that emit LLVM-IR (Nim, etc.). Is there any documentation of compiler configuration files that can be made public that would help with the development of an LLVM backend for the ESP32?

Another route to getting Rust (and other languages) compiling is to cross-compile them to C.

A follow up language-agnostic question relates to how peripheral drivers will be created. In the ARM world, there exists CMSIS specified SVD (System View Description) files that describe the peripheral control registers of the device, in terms of their base address, read/write permissions and bit-layout of each register including reserved bits and more information, all in an XML format. This allows programmatic generation of safe abstractions to access the registers, as opposed to simply writing to memory addresses. I understand that this is what ESP-IDF is attempting to provide (and more) (an example tool in Rust is https://crates.io/crates/svd2rust).
Does there exist an SVD file for this device or equivalent that could be used?


I'm interested in any and all discussion and information for the support of other compiled programming languages (excluding the scourge of javascript that seemingly must be run everywhere) on the ESP32.

I am not sure what you mean by 'compiler configuration files'... In GCC, Xtensa backend doesn't have much standalone documentation, as far as I know, but the code is relatively easy to follow. We are working with Cadence to make the official release of ISA reference manual possible, but there are some copies of it on the Internet which can be easily found with Google.
The processor-specific configuration overlay used in GCC build process is not specifically documented, but most configuration options are named in a very similar way to the ISA document. Instruction format files are also part of configuration overlay, and are used in binutils build process. Their format is not Xtensa-specific. I don't know if there is any tool which would assist in their conversion into LLVM .td files though.
By the way, if someone has LLVM experience and is interested in working on Xtensa support, please contact me.

Regarding register descriptions, we do have them an a machine readable format. It's not detailed enough to provide enumerations for individual fields (possible values are sometimes mentioned in human readable description, but this is not the case for all the registers).
There are a few problems which need to be addressed, like filtering out all registers which we don't want to document from these files, and unifying formats (different peripherals use slightly different formats), but I'm sure these can be solved.

Thanks for the reply, good to know that there's internal interest in releasing as much documentation as possible!
By compiler configuration files, I was referring to whatever customised files Cadence gives you when licensing a particularly configured Xtensa core. I don't really know the specifics, but you seemed to have covered most of that with your response, so no issue there.

As far as finding more information on the LX6 core, I was able to find "core-isa.h" in the distributed xtensa compiler. It makes reference to "core.h" which apparently contains more information, but I wasn't able to locate. Is this file public?

Also, is there a rough timeline as to when the machine-readable register descriptions will be available?

Thanks

ESP_igrr wrote:By the way, if someone has LLVM experience and is interested in working on Xtensa support, please contact me.

I haven't found a way to contact you through the forum; please send an email to whitequark@whitequark.org if you want to discuss this.

lberezy:
Configuration overlay is public, you can grab a copy here: https://github.com/jcmvbkbc/crosstool-N ... _esp32.tar

Regarding register documentation release, I'll discuss this internally and update this thread.

whitequark: thanks, sending you an email

Can somebody please post some update? What is the current status of the LLVM backend for Xtensa? Is there any way to track the progress with this? (Github, Twitter, etc.)

Sadly, after all this time I can say that there was no significant progress on this.

Is there a repo somewhere? A lower barrier to entry might help get other people onboard.
A project layout and a rought idea what the missing parts are would go a long way.

Is the register window handling already implemented? That stuff scares me the most.

I just published a script for compiling an ESP8266 firmware written in Rust (using mrustc to convert it to C). I'd be happy to receive a pull request adding support for ESP32.

https://github.com/emosenkis/esp-rs

Any chance of getting this to run in Julia and not rust?