Design question - sampling a relatively low frequency protocol
Posted: Sat Nov 09, 2024 7:40 pm
Hi,
I need to sample and decode a proprietary protocol. It consists of packets arriving at about 700 bits/ Second, and I will need to capture pulses about 500 uS in duration. (Either a single High pulse, 2 High pulses , or 4 High pulses.)
I will likely use an ESP32-C6, running at 160Mhz. (I want to bridge this protocol to Zigbee, thus the C6)
My initial thoughts are to use an edge-triggered interrupt on a GPIO pin, and on the rising edge, start a GP Timer. Then on the falling edge, stop the timer, and write the pulse width to an RTOS Queue, for later handling by an RTOS thread.
Given the pulse width, I think that the ISR latency will not be a factor here.
Any of you more more experienced folk have any thoughts here? Is this a reasonable approach?
Thanks,
Con
I need to sample and decode a proprietary protocol. It consists of packets arriving at about 700 bits/ Second, and I will need to capture pulses about 500 uS in duration. (Either a single High pulse, 2 High pulses , or 4 High pulses.)
I will likely use an ESP32-C6, running at 160Mhz. (I want to bridge this protocol to Zigbee, thus the C6)
My initial thoughts are to use an edge-triggered interrupt on a GPIO pin, and on the rising edge, start a GP Timer. Then on the falling edge, stop the timer, and write the pulse width to an RTOS Queue, for later handling by an RTOS thread.
Given the pulse width, I think that the ISR latency will not be a factor here.
Any of you more more experienced folk have any thoughts here? Is this a reasonable approach?
Thanks,
Con