Ethernet PHY best practices for low cost design
Posted: Thu Jul 09, 2020 2:55 pm
Hi,
I'm currently designing a low-cost device which needs Ethernet connectivity. I selected the LAN8720A PHY for its availability and cost.
I understand the clocking of the PHY and MAC is a bit tricky and that there are a few possibilities.
The current documentation states 3 modes:
A. The PHY is clocked with a low cost 25MHz crystal and derive a 50MHz clock to the ESP32 GPIO0.
B. Both the PHY and the MAC are clocked with an expensive 50MHz oscillator.
C. The MAC outputs the 50MHz clocks using either GPIO0, GPIO16 or GPIO17.
I understand the solution C is the lowest cost one(only 1 GPIO is used, no crystal, no oscillator, no special circuit to disable clocking during GPIO0 strap sampling). I wanted to confirm that this solution is considered stable and can be implemented in an actual product. Using GPIO0 to output the clocks is marked as experimental. Is it also the case for GPIO16 and 17? Is there a functional difference between using GPIO16/17 and GPIO0 ? I understand the clock is generated using an internal PLL system. Does it restrict other internal usage in this case?
Solution A. would be an alternative because it is not much more expensive (still only one GPIO used and the 25MHz crystal costs ~$0.05). The documentation warns about the fact that when held in reset, some PHY might still output the 50MHz clock and thus interfere in the boot process (GPIO0 strap sampling). Is it the case for the LAN8720A? Or this solution can be used safely?
Solution B is the most expensive (a 50MHz oscillator costs around $0.30 and I need an additional GPIO to control the enable line of the oscillator). What are the advantages of using this solution? I suspect it might be more robust but I'm not really sure.
Thanks in advance for any help and advice on using Ethernet with the ESP32.
I'm currently designing a low-cost device which needs Ethernet connectivity. I selected the LAN8720A PHY for its availability and cost.
I understand the clocking of the PHY and MAC is a bit tricky and that there are a few possibilities.
The current documentation states 3 modes:
A. The PHY is clocked with a low cost 25MHz crystal and derive a 50MHz clock to the ESP32 GPIO0.
B. Both the PHY and the MAC are clocked with an expensive 50MHz oscillator.
C. The MAC outputs the 50MHz clocks using either GPIO0, GPIO16 or GPIO17.
I understand the solution C is the lowest cost one(only 1 GPIO is used, no crystal, no oscillator, no special circuit to disable clocking during GPIO0 strap sampling). I wanted to confirm that this solution is considered stable and can be implemented in an actual product. Using GPIO0 to output the clocks is marked as experimental. Is it also the case for GPIO16 and 17? Is there a functional difference between using GPIO16/17 and GPIO0 ? I understand the clock is generated using an internal PLL system. Does it restrict other internal usage in this case?
Solution A. would be an alternative because it is not much more expensive (still only one GPIO used and the 25MHz crystal costs ~$0.05). The documentation warns about the fact that when held in reset, some PHY might still output the 50MHz clock and thus interfere in the boot process (GPIO0 strap sampling). Is it the case for the LAN8720A? Or this solution can be used safely?
Solution B is the most expensive (a 50MHz oscillator costs around $0.30 and I need an additional GPIO to control the enable line of the oscillator). What are the advantages of using this solution? I suspect it might be more robust but I'm not really sure.
Thanks in advance for any help and advice on using Ethernet with the ESP32.