ESP32 Forum

I read that the ESP32 has a RTC but where is its Vbatt supply pin when the main Vdd fails?

Has an rtc but not a battery-backed rtc. So you have to implement battery switching and sleep/wake in external circuitry and software.

You can connect both battery and main supply to the RTC via a couple of diodes (or a more complex switching circuit).

ESP_igrr wrote:You can connect both battery and main supply to the RTC via a couple of diodes (or a more complex switching circuit).

Does battery have to also connect to VDD3P3_CPU since

VDD3P3_CPU is also the input power supply for CPU

or is it OK to cut power to VDD3P3_CPU but not VDD3P3_RTC?

Depending on what is the goal... If the goal is to keep just the RTC working in the event of loss of power, then powering VDD3P3_RTC with a battery-backed supply is enough. If the goal is to also save main memory contents, then VDD3P3_CPU should be battery-backed as well (although this will likely need a much bigger battery).

ESP_igrr wrote:Depending on what is the goal... If the goal is to keep just the RTC working in the event of loss of power, then powering VDD3P3_RTC with a battery-backed supply is enough. If the goal is to also save main memory contents, then VDD3P3_CPU should be battery-backed as well (although this will likely need a much bigger battery).

So power to VDD3P3_CPU dies, chip_pu goes low, VDD3P3_RTC stays high, chip is in lowest power state, VDD3P3_RTC keeps rtc powered up, rtc io and rtc fast/slow ram are ...on/off? After chip_pu goes high and spurious wdt reset rtc is still ticking and accurate?

Or we have to detect power failure, keep CPU active on battery long enough to enter deep sleep (can we enter deep sleep from ISR?), enable wake on detect power restored, and keep rtc fast mem powered up to avoid spurious wdt reset?

Good point about CH_PD... let me do some tests, will get back on this.

Did a few tests about this. The issue seems to be that internal CPU regulator can also take power from VDD_RTC pin, meaning that if all the power rails except VDD_RTC are powered off, CPU can still keep running; this may cause issues if the CPU tries to read instructions or data from Flash, which will be powered down. This will soon cause the CPU to crash and enter boot loop.

Monitoring the VDD and going into deep sleep when it disappears is possible, but we are looking for an automatic solution to the problem.

OK, following topic.

ESP_igrr wrote:Did a few tests about this. The issue seems to be that internal CPU regulator can also take power from VDD_RTC pin, meaning that if all the power rails except VDD_RTC are powered off, CPU can still keep running; this may cause issues if the CPU tries to read instructions or data from Flash, which will be powered down. This will soon cause the CPU to crash and enter boot loop.

Monitoring the VDD and going into deep sleep when it disappears is possible, but we are looking for an automatic solution to the problem.

hi any update on this... we need to implement this in one of our projects. could we get a timeline on when will this feature be implemented.

Regards

Rickson.