Small ESP32 Modul ( all include in new ESP32-PICO )

[rudi ;-)]

step result:

qio_mode_fallback_DIO.png (28.96 KiB) Viewed 20688 times

I conclude at first that the SPI Flash internally work only in DIO and is not compare with D2WD.
edit: See this post, it falls back cause used bootloader from "future/psram_malloc" ( PICO-D4 added )

[rudi ;-)]

That looks like the same arrangement of pins as in D2WD, is it not?

ESP32-D2WD’s pins GPIO16,GPIO17,SD_CMD,SD_CLK,SD_DATA_0 and SD_DATA_1 are used for connecting the embedded flash, and are not recommended for other uses.

next step result ( which pins are really used in the SIP ) :

Code: Select all

SPI_PAD_CONFIG_CLK     Override SD_CLK pad (GPIO6/SPICLK)                = 6 R/W (0x6)
SPI_PAD_CONFIG_Q       Override SD_DATA_0 pad (GPIO7/SPIQ)               = 17 R/W (0x11)
SPI_PAD_CONFIG_D       Override SD_DATA_1 pad (GPIO8/SPID)               = 8 R/W (0x8)
SPI_PAD_CONFIG_HD      Override SD_DATA_2 pad (GPIO9/SPIHD)              = 11 R/W (0xb)
SPI_PAD_CONFIG_CS0     Override SD_CMD pad (GPIO11/SPICS0)               = 16 R/W (0x10)

you can use simply efuse check for this

check-fuses.png (38.13 KiB) Viewed 20684 times

good to know - cause - pSRAM is with this just in time not possible ( not with the just in time future/psram-malloc )
cause pSRAM used IO16, IO17 for pSRAM CS and pSRAM CLK.

so we can save the theme pSRAM on SIP for later time and test it again with esp-idf-3.0 branch after merging pSRAM


txs for your helps


best wishes
rudi

[rudi ;-)]

mhm..
but what is, if we "knock out" the packaged 4MB SPI flash and connect extern 128Mbit on standard pins.
we refuse the pin assigment and can connect pSRAM on usually pins cs io16, clk io17.
sure - all must be done with same power supply like the packaged SPI flash, cause VDD_SDIO is VDD_SDIO_NC
hope the packaged spi flash do not disturb the lines on io16, io17.
perhabs i will have a try with this for fun - perhabs.

[rudi ;-)]

see a chance

the SPI Flash was bonding on this and fused:

Code: Select all

SPI_PAD_CONFIG_CLK     Override SD_CLK pad (GPIO6/SPICLK)                = 6 R/W (0x6)
SPI_PAD_CONFIG_Q       Override SD_DATA_0 pad (GPIO7/SPIQ)               = 17 R/W (0x11)
SPI_PAD_CONFIG_D       Override SD_DATA_1 pad (GPIO8/SPID)               = 8 R/W (0x8)
SPI_PAD_CONFIG_HD      Override SD_DATA_2 pad (GPIO9/SPIHD)              = 11 R/W (0xb)
SPI_PAD_CONFIG_CS0     Override SD_CMD pad (GPIO11/SPICS0)               = 16 R/W (0x10)

we have no IO16, IO17 for pSRAM, but we "get" IO09 and IO10 and
this are silked on the PCB and i can toggle this pins over GPIO Pad.

so this 2 pins becomes then the /CS and CLK for pSRAM later and they are in the VDD_SDIO Domain

the SD0, SD1, SD2, SD3 is silked too and i hope that they are like they fused:
SD0(IO7) = now IO17 as silked SD0
SD1(IO8) = let it IO8 as silked SD1
SD2(IO9) = now IO11 as silked SD2
SD3(IO7) = let it IO07 as silked SD3 ( /WP menuconfig )

now we are near complet

we need GND
we need VDD_SDIO

cause VDD_SDIO is not break out on SIP ( VDD_SDIO_NC ) and
cause with bootstrap MTDI HIGH ( 1.8 ) the boot fails,
it must be a 3.3V SPI Flash, so we need 3.3V pSRAM and we can
then connect on 3.3V.

2 unhappy things are:
a) SOC is Rev0 so we need to note ECO and Workarounds for Bugs in ESP32
b) we need for deep sleep if we want power of pSRAM too, switching 3.3V, cause VDD_SDIO is not break out on SoC like shematic says.

cause this are "testmodules" i see it for a) so, that later comes out this module, if marketing gives ok, modules with rev1 or later.
for b) there can perhabs comes a change or not.

the try is prepaired for coming weekend.

edit: insert picture

suggestion-proposal.png (26.39 KiB) Viewed 20598 times

let see what happens, hope the bonding was noted "high speed rules"
cause the lines can disturb pSRAM lines. same for pSRAM lines to flash lines.


btw:
i think we can connect easy with IO9, IO10 more SPI Fash too, if we not use extern pSRAM IC.

best wishes
rudi

[rudi ;-)]

ESP32-PICO-D4
ESP32_PICO_Core_Board_V2
PSRAM 3.3V 64MBit ( 32MBit used )
done!
rudi
--------------------------------------------------------

IMG_8394_s.jpg (94.65 KiB) Viewed 20520 times

ets Jun 8 2016 00:22:57

rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0008,len:4
load:0x3fff000c,len:4376
load:0x40078000,len:11100
load:0x40080000,len:252
entry 0x40080034
I (46) boot: ESP-IDF 2nd stage bootloader
I (46) boot: compile time 00:45:30
I (46) boot: Enabling RNG early entropy source...
I (58) boot: SPI Speed : 40MHz
I (71) boot: SPI Mode : DIO
I (83) boot: SPI Flash Size : 4MB
I (95) boot: Partition Table:
I (107) boot: ## Label Usage Type ST Offset Length
I (129) boot: 0 nvs WiFi data 01 02 00009000 00006000
I (152) boot: 1 phy_init RF data 01 01 0000f000 00001000
I (176) boot: 2 factory factory app 00 00 00010000 00100000
I (199) boot: End of partition table
I (212) boot: Disabling RNG early entropy source...
I (229) boot: Loading app partition at offset 00010000
I (507) boot: segment 0: paddr=0x00010018 vaddr=0x3ffb0000 size=0x01bac ( 7084) load
I (511) boot: segment 1: paddr=0x00011bcc vaddr=0x40080000 size=0x00400 ( 1024) load
I (525) boot: segment 2: paddr=0x00011fd4 vaddr=0x40080400 size=0x08238 ( 33336) load
I (567) boot: segment 3: paddr=0x0001a214 vaddr=0x400c0000 size=0x00000 ( 0) load
I (577) boot: segment 4: paddr=0x0001a21c vaddr=0x00000000 size=0x05de4 ( 24036)
I (602) boot: segment 5: paddr=0x00020008 vaddr=0x3f400010 size=0x03078 ( 12408) map
I (628) boot: segment 6: paddr=0x00023088 vaddr=0x00000000 size=0x0cf80 ( 53120)
I (653) boot: segment 7: paddr=0x00030010 vaddr=0x400d0018 size=0x0d3ac ( 54188) map
I (681) cpu_start: PSRAM mode: flash 40m sram 40m
I (695) cpu_start: PSRAM initialized, cache is in even/odd (2-core) mode.
I (718) cpu_start: Pro cpu up.
I (730) cpu_start: Starting app cpu, entry point is 0x40080dd0
I (0) cpu_start: App cpu up.
I (762) heap_alloc_caps: Initializing. RAM available for dynamic allocation:
I (785) heap_alloc_caps: At 3F800000 len 00400000 (4096 KiB): SPIRAM
I (806) heap_alloc_caps: At 3FFAE2A0 len 00001D60 (7 KiB): DRAM
I (827) heap_alloc_caps: At 3FFB2370 len 0002DC90 (183 KiB): DRAM
I (847) heap_alloc_caps: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM
I (869) heap_alloc_caps: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (890) heap_alloc_caps: At 40088638 len 000179C8 (94 KiB): IRAM
I (911) cpu_start: Pro cpu start user code
I (968) cpu_start: Starting scheduler on PRO CPU.
I (221) cpu_start: StarRtAMi innitg do nes
cheduler on APP CPU.
reserved: 16
len of my PSRAM Buffer is: 4194297
delay pico-d4
delay pico-d4
delay pico-d4
delay pico-d4
delay pico-d4
ets Jun 8 2016 00:22:57

rst:0x1 (POWERON_RESET),boot:0x3 (DOWNLOAD_BOOT(UART0/UART1/SDIO_REI_REO_V2))
waiting for download

psram.c

Code: Select all

#define PICO 1

#ifdef PICO
#define PSRAM_CS_IO        9
#define PSRAM_CLK_IO       10
#else
#define PSRAM_CS_IO        16
#define PSRAM_CLK_IO       17
#endif

psram.c
"psram_gpio_config"

Code: Select all

#ifdef PICO
	/* TEST Config for the PICO-D4
		 * - ESP32_PICO_Core_Board_V2
		 * - ESP32_PICO_Core_Board_V3
		 * Note: V2 & V3 Boards have ESP32 Rev=0
		 * psram_enable works correctly only with v1 (post Feb 2017) and later ESP32 revisions.
		 * 29 August 2017 rudi ;-)
		 */
	/* SPICS0 CS */
	gpio_matrix_out(16, SPICS0_OUT_IDX, 0, 0); //11
    /* SPICLK CLK */
	gpio_matrix_out(6, SPICLK_OUT_IDX, 0, 0);
    /* SPIQ alias SD0 */
    gpio_matrix_out(17, SPIQ_OUT_IDX, 0, 0);   // 7
    gpio_matrix_in(17,SPIQ_IN_IDX, 0);         // 7
    /* SPID alias SD1 */
    gpio_matrix_out(8, SPID_OUT_IDX, 0, 0);
    gpio_matrix_in(8, SPID_IN_IDX, 0);
    /* SPIHD HOLD alias SD2 */
    gpio_matrix_out(11, SPIHD_OUT_IDX, 0, 0); // 9
    gpio_matrix_in(11, SPIHD_IN_IDX, 0);      // 9
    /* WP alias SD3 */
    gpio_matrix_out(7, SPIWP_OUT_IDX, 0, 0); // 10 a try with 7 like D2WD
    gpio_matrix_in(7, SPIWP_IN_IDX, 0);      // 10 a try with 7 like D2WD

#else

    gpio_matrix_out(6, SPICLK_OUT_IDX, 0, 0);
    gpio_matrix_out(11, SPICS0_OUT_IDX, 0, 0);
    gpio_matrix_out(7, SPIQ_OUT_IDX, 0, 0);
    gpio_matrix_in(7,SPIQ_IN_IDX, 0);
    gpio_matrix_out(8, SPID_OUT_IDX, 0, 0);
    gpio_matrix_in(8, SPID_IN_IDX, 0);
    gpio_matrix_out(10, SPIWP_OUT_IDX, 0, 0);
    gpio_matrix_in(10, SPIWP_IN_IDX, 0);
    gpio_matrix_out(9, SPIHD_OUT_IDX, 0, 0);
    gpio_matrix_in(9, SPIHD_IN_IDX, 0);
#endif

freertos/heap_regions.c
"vPortFreeTagged"

Code: Select all

        /* Check the block is actually allocated. */
        configASSERT( ( pxLink->xAllocated ) != 0 );
        // configASSERT( pxLink->pxNextFreeBlock == NULL );  // note: customized by rudi so please wait for the ESP-IDF 3.0 what they do :)  

now - i am very happy.

- PICO support extern PSRAM now done. ( but note! Supply is done by 3.3 not by VDD_SDIO cause VDD_SDIO is NC. )

customized future\psram_malloc for
- D2WD - done
- PICO - done
so TBD was done now too guys

now - i am really enjoy the last days from holidays.
my homework was done
thank you espressif! for Pico Board V2 and V3
had many fun and enjoyed the results.

@john lee
- 3.3V runs like a clock work btw
- D2WD and PICO psram support by user



best wishes
rudi

[WiFive]

So PICO samples are rev0 but will all production PICO have rev1?

[rudi ;-)]

So PICO samples are rev0 but will all production PICO have rev1?

Hi WiFive,
hope you are ok/enjoyed your holiday
I've missed you already.

Just in time not for sale.
but you can get samples

V2 is KIV

Marketing is still considering whether it will be a product,
and which form factor.

best wishes
rudi

[rudi ;-)]

thanks for updating

revised_v1.0_31.08.2017.png (13.28 KiB) Viewed 20436 times

ESP32-PICO-D4 datasheet V1.0 from 31. August 2017

esp32-pico-d4_datasheet_en_V1.0_vom_31.08.2017.pdf

ESP32-PICO-D4 Datasheet V1.0
revised 31 August 2017

(716.72 KiB) Downloaded 1138 times

src now online again

best wishes
rudi

[playflash]

thanks for updating

revised_v1.0_31.08.2017.png

ESP32-PICO-D4 datasheet V1.0 from 31. August 2017

esp32-pico-d4_datasheet_en_V1.0_vom_31.08.2017.pdf

src now online again

best wishes
rudi

Hi, rudi,
I must say you did a great job here.
So, an External PSRAM work with these two chips.
- D2WD
- PICO
Can you tell me what PSRAM you tested? And where to buy them if you know?
It is pity that espressif didn't put a PSRAM in PICO.
Thank you very much.

[ESP_igrr]

Please note that PICO and D2WD are not supported in combination with PSRAM yet:
https://github.com/espressif/esp-idf/bl ... #L480-L489