SPI sck synchronization

[qwertyuio]

Hi! I'm using a esp32-WROVER-IE and Arduino IDE for programming. I'm trying to read from the Intan RHD Recording Headstages, which send data on both the rising end falling edge of the SCK. To read during the rising and falling edge, I'm trying to use both VSPI and HSPI, but delay one of the SCK by half a cycle, so that when one SCK is on the rising edge, the other is falling and vise versa to read all the data send by the RHD recording headstage.

When I try to measure both VSPI and HSPI SCK with an oscilloscope, I noticed that the SCK isn't always sending signals, rather it's alternating between flattening and sending SCK signals, and when one SPI is flattening, the other is sending the signals. (image attached below to show what I mean). Is that just how SCK work or is there a delay in the code that I didn't realize? is there a way to make both SCK send signals at the same time? (code attached below)

Also, I'm thinking to add a delay() between the spi.begin to do what I mentioned above. Is that possible? And is there potentially a better and more efficient solution?

Here's the code that I'm using to measure the SCK. It's given to me as an esp32-WROVER example in Arduino IDE
#include <SPI.h>

// Define ALTERNATE_PINS to use non-standard GPIO pins for SPI bus

#ifdef ALTERNATE_PINS
#define VSPI_MISO 19
#define VSPI_MOSI 23
#define VSPI_SCLK 18
#define VSPI_SS 5

#define HSPI_MISO 12
#define HSPI_MOSI 13
#define HSPI_SCLK 14
#define HSPI_SS 15
#else
#define VSPI_MISO MISO
#define VSPI_MOSI MOSI
#define VSPI_SCLK SCK
#define VSPI_SS SS

#define HSPI_MISO 12
#define HSPI_MOSI 13
#define HSPI_SCLK 14
#define HSPI_SS 15
#endif

#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#define VSPI FSPI
#endif

static const int spiClk = 1000;

//uninitialised pointers to SPI objects
SPIClass *vspi = NULL;
SPIClass *hspi = NULL;

void setup() {
//initialize two instances of the SPIClass attached to VSPI and HSPI respectively
vspi = new SPIClass(VSPI);
hspi = new SPIClass(HSPI);

//clock miso mosi ss

#ifndef ALTERNATE_PINS
//initialize vspi with default pins
//SCLK = 18, MISO = 19, MOSI = 23, SS = 5
vspi->begin();
#else
//alternatively route through GPIO pins of your choice
vspi->begin(VSPI_SCLK, VSPI_MISO, VSPI_MOSI, VSPI_SS); //SCLK, MISO, MOSI, SS
#endif

#ifndef ALTERNATE_PINS
//initialize hspi with default pins
//SCLK = 14, MISO = 12, MOSI = 13, SS = 15
hspi->begin();
#else
//alternatively route through GPIO pins
hspi->begin(HSPI_SCLK, HSPI_MISO, HSPI_MOSI, HSPI_SS); //SCLK, MISO, MOSI, SS
#endif

//set up slave select pins as outputs as the Arduino API
//doesn't handle automatically pulling SS low
pinMode(vspi->pinSS(), OUTPUT); //VSPI SS
pinMode(hspi->pinSS(), OUTPUT); //HSPI SS
digitalWrite(vspi->pinSS(), LOW);
digitalWrite(hspi->pinSS(), LOW);
}

// the loop function runs over and over again until power down or reset
void loop() {
//use the SPI buses
spiCommand(vspi, 0b01010101); // junk data to illustrate usage
spiCommand(hspi, 0b11001100);
}

void spiCommand(SPIClass *spi, byte data) {
//use it as you would the regular arduino SPI API
spi->beginTransaction(SPISettings(spiClk, MSBFIRST, SPI_MODE0));
//digitalWrite(spi->pinSS(), LOW); //pull SS slow to prep other end for transfer
spi->transfer(data);
//digitalWrite(spi->pinSS(), HIGH); //pull ss high to signify end of data transfer
spi->endTransaction();
}

[ESP_Sprite]

If you have that option, you could consider switching to an ESP32-S3. The 'using both rising and falling edges' is called 'DDR' and the S3 supports that natively. (Although I'm not sure if the Arduino SPI SDK does; you may need to use the ESP-IDF SPI driver instead.)

Alternatively, if you still can change the hardware, you could add a simple D flipflop (e.g. a 74LVC1G74) to divide the SCLK by half.

[qwertyuio]

Thank you for your help! I'll try out your solutions and hopefully it works!

[qwertyuio]

Hi, did some more research into the esp32 s3 chip, and I have a few questions.

First, what does the 8 line DDR mode mean? does that mean there's 8 parallel data lines like MISO1, MISO2, MISO3, and MISO4, as well as MOSI1, MOSI2, MOSI3, and MOSI4?

Secondly, can the SPI buses be configured so that CS is held low for each SPI word, then set high for a sufficient period (at least 154 ns) to satisfy the timing requirements of the RHD2164 SPI? Or do I have to using a manually toggled GPIO to act as CS?

And lastly, what about the time delay between CS going low and the first SCLK pulse - is that configurable to make sure at least 20.8 ns occurs?

also, is there a user manual or similar document goes more in-depth into each peripheral? The datasheet gives a general overview but is there any documentation that's more specific and more detailed, that would be very helpful so I can look up the answers myself.

Again, thank you so much for your help!

[ESP_Sprite]

Hi, did some more research into the esp32 s3 chip, and I have a few questions.

First, what does the 8 line DDR mode mean? does that mean there's 8 parallel data lines like MISO1, MISO2, MISO3, and MISO4, as well as MOSI1, MOSI2, MOSI3, and MOSI4?

That is octal SPI and it more-or-less orthoginal to DDR. DDR affects the clock, octal SPI affects the bus width.

Secondly, can the SPI buses be configured so that CS is held low for each SPI word, then set high for a sufficient period (at least 154 ns) to satisfy the timing requirements of the RHD2164 SPI? Or do I have to using a manually toggled GPIO to act as CS?

Not sure. You may need to send each byte as a separate transaction.

And lastly, what about the time delay between CS going low and the first SCLK pulse - is that configurable to make sure at least 20.8 ns occurs?

I think we have knobs for that.

also, is there a user manual or similar document goes more in-depth into each peripheral? The datasheet gives a general overview but is there any documentation that's more specific and more detailed, that would be very helpful so I can look up the answers myself.

I think you're looking for the technical reference manual.

[qwertyuio]

Hi, on the esp32-s3 datasheet v1.8, it says "• 8-line SPI mode supports single data rate (SDR) and double data rate (DDR)" (page 36 at the bottom under the "Features of SPI0 and SPI1" section). https://www.espressif.com/sites/default ... eet_en.pdf

Does that mean that DDR can only be accessed through 8-line SPI mode? Or would it work with just one MISO and one MOSI?

Also, the technical manual doesn't give much details on the SPI0 and SPI1, so it is even possible to connect them to another device with SPI and send data that way? Or is it just like a internal chip thing that I can't access.

More details would be good. I'm a beginner with esp32 and SPI systems.

Edit: I just got the esp32-s3 wroom-1 dev board. when using the esp-idf command prompt, I can only turn on the DDR flash sampling mode when I check the "enable Octal flash". Does octal flash use 4 MOSI and 4 MISO or does it also work with 1 MOSI and 1 MISO?

[ESP_Sprite]

Hi, on the esp32-s3 datasheet v1.8, it says "• 8-line SPI mode supports single data rate (SDR) and double data rate (DDR)" (page 36 at the bottom under the "Features of SPI0 and SPI1" section). https://www.espressif.com/sites/default ... eet_en.pdf

Does that mean that DDR can only be accessed through 8-line SPI mode? Or would it work with just one MISO and one MOSI?

Also, the technical manual doesn't give much details on the SPI0 and SPI1, so it is even possible to connect them to another device with SPI and send data that way? Or is it just like a internal chip thing that I can't access.

Please ignore SPI0/1 as they're connected to flash and PSRAM and as such not useful for your purpose. You need to use SPI2. Note that the DDR feature there is not very well documented aside from the bits you need to set. Your best bet would be to use the standard ESP-IDF driver and set SPI_DEVICE_DDRCLK on the device flags, btw.

[qwertyuio]

Thank you for the suggestion. I'm trying to use SPI and read from the intan RDH headstage with 128 channels, here's the datasheet: https://intantech.com/files/Intan_RHD20 ... dstage.pdf
And here's the adapter board I'm using to connect the headstage to the microcontroller :
https://intantech.com/files/Intan_LVDS_ ... _board.pdf
Because it has 128 channels, it uses 2 MISO lines (MISO1 and MISO2), and each send data from 64 channels, and it looks like I need to read from both MISO lines. Do I have to use both SPI2 and SPI3 in order to read from both MISO or is there some configuration that I can set to read from 2 MISO using only 1 SPI?