"Access cache when cache is disabled" exception on ESP32-S3-EYE?

[Polarbear17123]

Hello,
I am getting an "access cache when cache is disabled" exception on ESP32-S3-EYE.
I am using the PSRAM and it may be related.
Did anyone see this before and knows how to fix the issue?
Thank you!

[ESP_Sprite]

Most likely cause is you having an interrupt marked as being entirely in IRAM which then accesses flash or psram.

[MicroController]

Adding to that, the cache is disabled during writes to flash memory (NVS, partition API, filesystem,...). So the error commonly occurs when an interrupt is handled while a flash write operation is ongoing and the code executed and/or data accessed by the ISR does not (completely) reside in internal RAM ("IRAM"). Solution is to either make sure the ISR runs from IRAM only, or not (erroneously) have the interrupt allocated with ESP_INTR_FLAG_IRAM set.

[Polarbear17123]

I am running TF Micro, the PSRAM is used to allocate the tensor area, No code.
Can this interrupt be a page-fault? (assuming paging is enabled in Free-RTOS) ?

[ESP_Sprite]

No, the ESP32-S3/ESP-IDF don't do page faulting; all memory pages are always available.

If you can post the error log (including the backtrace) and/or your code, we may be able to tell you more.