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esp32-s3 i2c failure in esp-idf 5.2

http://forum.esp32.com/viewtopic.php?f=13&t=38725

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esp32-s3 i2c failure in esp-idf 5.2

Posted: Tue Mar 05, 2024 2:25 am
by sb_espressif
Hi;

I recently upgraded my setup from esp-idf 5.1.2 to 5.2, and am trying to write a driver for a magnetic encoder that configures the chip via i2c. This code/driver runs fine on an esp32-c3 seeed module I have, but crashes the same way on two different esp32-s3 boards I've tried. I don't understand the error that's being offered. I am using:

Code: Select all

#include "driver/i2c_master.h"
and the problematic code is:

Code: Select all

    // Per these docs:
    // https://docs.espressif.com/projects/esp-idf/en/v5.2/esp32/api-reference/peripherals/i2c.html#i2c_master_controller
    // We are configuring the i2c master bus first.
    i2c_master_bus_config_t i2c_master_config = {
        .clk_source = I2C_CLK_SRC_DEFAULT,
        .i2c_port = I2C_MASTER_PORT,
        .scl_io_num = I2C_MASTER_SCL_IO,        // SCL pin
        .sda_io_num = I2C_MASTER_SDA_IO,        // SCL pin
        .glitch_ignore_cnt = 7,                 // a default from esp's docs
        .flags.enable_internal_pullup = true,
    };

    i2c_master_bus_handle_t bus_handle;
    i2c_new_master_bus(&i2c_master_config, &bus_handle);
Specifically, the complaint is on the final line there, where I create a new i2c master bus.

Code: Select all

assert failed: xTaskRemoveFromEventList tasks.c:3826 (pxUnblockedTCB)


Backtrace: 0x403758e2:0x3fc9a2b0 0x40379ed1:0x3fc9a2d0 0x40380371:0x3fc9a2f0 0x4037bec2:0x3fc9a410 0x4037a744:0x3fc9a430 0x4037a7f6:0x3fc9a470 0x40376865:0x3fc9a490 0x40376945:0x3fc9a4c0 0x420082b3:0x3fc9a4e0 0x42006e61:0x3fc9a500 0x420069d2:0x3fc9a520 0x4200f77e:0x3fc9a540 0x4200ef4d:0x3fc9a560 0x4200efaa:0x3fc9a580 0x4200f5e9:0x3fc9a5b0 0x420136b7:0x3fc9a5e0 0x4201307a:0x3fc9a600 0x4200f7f5:0x3fc9a920 0x4201b565:0x3fc9a950 0x403800e5:0x3fc9a980 0x42009b8d:0x3fc9a9d0 0x4200b6fe:0x3fc9aa30 0x4200a925:0x3fc9aa90 0x4200ae88:0x3fc9aac0 0x4200834c:0x3fc9ab10 0x4037a8c1:0x3fc9ab60
0x403758e2: panic_abort at /Users/me/dev/github/esp-idf-v5.2/components/esp_system/panic.c:472
0x40379ed1: esp_system_abort at /Users/me/dev/github/esp-idf-v5.2/components/esp_system/port/esp_system_chip.c:93
0x40380371: __assert_func at /Users/me/dev/github/esp-idf-v5.2/components/newlib/assert.c:81
0x4037bec2: xTaskRemoveFromEventList at /Users/me/dev/github/esp-idf-v5.2/components/freertos/FreeRTOS-Kernel/tasks.c:3826 (discriminator 1)
0x4037a744: xQueueSemaphoreTake at /Users/me/dev/github/esp-idf-v5.2/components/freertos/FreeRTOS-Kernel/queue.c:1763
0x4037a7f6: xQueueTakeMutexRecursive at /Users/me/dev/github/esp-idf-v5.2/components/freertos/FreeRTOS-Kernel/queue.c:835
0x40376865: lock_acquire_generic at /Users/me/dev/github/esp-idf-v5.2/components/newlib/locks.c:144
0x40376945: _lock_acquire_recursive at /Users/me/dev/github/esp-idf-v5.2/components/newlib/locks.c:158
0x420082b3: uart_write at /Users/me/dev/github/esp-idf-v5.2/components/vfs/vfs_uart.c:209
0x42006e61: console_write at /Users/me/dev/github/esp-idf-v5.2/components/vfs/vfs_console.c:73 (discriminator 1)
0x420069d2: esp_vfs_write at /Users/me/dev/github/esp-idf-v5.2/components/vfs/vfs.c:482 (discriminator 4)
0x4200f77e: __swrite at /builds/idf/crosstool-NG/.build/HOST-x86_64-apple-darwin21.1/xtensa-esp-elf/src/newlib/newlib/libc/stdio/stdio.c:94
0x4200ef4d: __sflush_r at /builds/idf/crosstool-NG/.build/HOST-x86_64-apple-darwin21.1/xtensa-esp-elf/src/newlib/newlib/libc/stdio/fflush.c:224
0x4200efaa: _fflush_r at /builds/idf/crosstool-NG/.build/HOST-x86_64-apple-darwin21.1/xtensa-esp-elf/src/newlib/newlib/libc/stdio/fflush.c:278
 (inlined by) _fflush_r at /builds/idf/crosstool-NG/.build/src/newlib-git-af24ceb7/newlib/libc/include/stdio.h:417
0x4200f5e9: __sfvwrite_r at /builds/idf/crosstool-NG/.build/HOST-x86_64-apple-darwin21.1/xtensa-esp-elf/src/newlib/newlib/libc/stdio/fvwrite.c:251
0x420136b7: __sprint_r at /builds/idf/crosstool-NG/.build/HOST-x86_64-apple-darwin21.1/xtensa-esp-elf/src/newlib/newlib/libc/stdio/vfiprintf.c:429
 (inlined by) __sprint_r at /builds/idf/crosstool-NG/.build/HOST-x86_64-apple-darwin21.1/xtensa-esp-elf/src/newlib/newlib/libc/stdio/vfprintf.c:399
0x4201307a: _vfprintf_r at /builds/idf/crosstool-NG/.build/HOST-x86_64-apple-darwin21.1/xtensa-esp-elf/src/newlib/newlib/libc/stdio/vfprintf.c:1774 (discriminator 1)
0x4200f7f5: vprintf at /builds/idf/crosstool-NG/.build/HOST-x86_64-apple-darwin21.1/xtensa-esp-elf/src/newlib/newlib/libc/stdio/vprintf.c:34
0x4201b565: esp_log_writev at /Users/me/dev/github/esp-idf-v5.2/components/log/log.c:215
0x403800e5: esp_log_write at /Users/me/dev/github/esp-idf-v5.2/components/log/log.c:225
0x42009b8d: gpio_config at /Users/me/dev/github/esp-idf-v5.2/components/driver/gpio/gpio.c:408 (discriminator 1)
0x4200b6fe: i2c_common_set_pins at /Users/me/dev/github/esp-idf-v5.2/components/driver/i2c/i2c_common.c:235
0x4200a925: i2c_param_master_config at /Users/me/dev/github/esp-idf-v5.2/components/driver/i2c/i2c_master.c:642
0x4200ae88: i2c_new_master_bus at /Users/me/dev/github/esp-idf-v5.2/components/driver/i2c/i2c_master.c:799
0x4200834c: i2c_scan_task at /Users/me/dev/esp/i2c-scan/main/i2c-scan.c:62
0x4037a8c1: vPortTaskWrapper at /Users/me/dev/github/esp-idf-v5.2/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c:134
I've tried specifying different pins for i2c, not sure what else to try to troubleshoot...

Re: esp32-s3 i2c failure in esp-idf 5.2

Posted: Tue Mar 05, 2024 11:07 am
by mikemoy
Try using the setup for the examples folder. It's a bit different than what you have.

https://github.com/espressif/esp-idf/bl ... ple_main.c

Re: esp32-s3 i2c failure in esp-idf 5.2

Posted: Tue Mar 05, 2024 3:25 pm
by sb_espressif
As I understand it, that setup uses a soon-to-be-deprecated way of communicating via i2c. The reason I think this is because my code actually WAS set up as exemplified in that link, and I saw a warning in the runtime messaging telling me the i2c.h header is outdated and to migrate to i2c_master.h.

In any case, both setups produce the same odd failure, despite being two totally different headers. This made me suspect maybe my board is just messed up, but I've tried two different esp32-s3's and both exhibit the same behavior.

I think my next test will be to downgrade back to esp-idf 5.1.2 to see if this failure persists...

Re: esp32-s3 i2c failure in esp-idf 5.2

Posted: Wed Mar 06, 2024 12:05 pm
by MicroController
The backtrace shows that your I2C setup is not the actual reason for the failure. The problem presumably occurs when the (GPIO) driver tries to log the new GPIO configuration via UART. Does logging (ESP_LOGx(...)) from your application work (prior to initializing the I2C)?

Also, the failing assertion indicates that something inside FreeRTOS's task management has become inconsistent.
This may or may not be due to some memory corruption, or some invalid use of FreeRTOS APIs.
Since your code apparently works on another SoC, I'd first try increasing the task's stack size. The issue could also depend on the timing/execution order of things which may be different between SoCs.

In the end, the code snippet you posted does give any information on what could actually be going wrong.

Re: esp32-s3 i2c failure in esp-idf 5.2

Posted: Wed Mar 06, 2024 2:41 pm
by sb_espressif
This is a great clue, thank you! TL;DR, I tried increasing my task allocation size from 2048 to 4096 and the error messages I was seeing went away. However, I still do not seem to be able to successfully communicate with an i2c device (whereas an identical circuit using a C3 and the same code does find the device I'm attaching).

To your point about painting an incomplete picture, you're right; here's some more info.

When I compile and run a simple "hello world" example, and install it on both an esp32-s3 and an esp32-c3, I see this (which I'm offering to help give context about the actual microcontrollers I'm testing with):

For the S3:

Code: Select all

I (26) boot: ESP-IDF v5.2 2nd stage bootloader
I (26) boot: compile time Mar  4 2024 20:10:03
I (26) boot: Multicore bootloader
I (29) boot: chip revision: v0.2
I (33) boot.esp32s3: Boot SPI Speed : 80MHz
I (38) boot.esp32s3: SPI Mode       : DIO
I (42) boot.esp32s3: SPI Flash Size : 2MB
I (47) boot: Enabling RNG early entropy source...
I (53) boot: Partition Table:
I (56) boot: ## Label            Usage          Type ST Offset   Length
I (63) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (71) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (78) boot:  2 factory          factory app      00 00 00010000 00100000
I (86) boot: End of partition table
I (90) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=0ce0ch ( 52748) map
I (108) esp_image: segment 1: paddr=0001ce34 vaddr=3fc91e00 size=028c0h ( 10432) load
I (110) esp_image: segment 2: paddr=0001f6fc vaddr=40374000 size=0091ch (  2332) load
I (116) esp_image: segment 3: paddr=00020020 vaddr=42000020 size=18684h ( 99972) map
I (142) esp_image: segment 4: paddr=000386ac vaddr=4037491c size=0d3e4h ( 54244) load
I (160) boot: Loaded app from partition at offset 0x10000
I (160) boot: Disabling RNG early entropy source...
I (171) cpu_start: Multicore app
I (181) cpu_start: Pro cpu start user code
I (181) cpu_start: cpu freq: 160000000 Hz
I (181) cpu_start: Application information:
I (184) cpu_start: Project name:     blink
I (189) cpu_start: App version:      1
I (193) cpu_start: Compile time:     Mar  4 2024 20:09:50
I (199) cpu_start: ELF file SHA256:  a6680a300...
I (204) cpu_start: ESP-IDF:          v5.2
I (209) cpu_start: Min chip rev:     v0.0
I (214) cpu_start: Max chip rev:     v0.99 
I (219) cpu_start: Chip rev:         v0.2
I (223) heap_init: Initializing. RAM available for dynamic allocation:
I (231) heap_init: At 3FC94F90 len 00054780 (337 KiB): RAM
I (237) heap_init: At 3FCE9710 len 00005724 (21 KiB): RAM
I (243) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
I (249) heap_init: At 600FE010 len 00001FD8 (7 KiB): RTCRAM
I (256) spi_flash: detected chip: gd
I (259) spi_flash: flash io: dio
W (263) spi_flash: Detected size(8192k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
I (277) sleep: Configure to isolate all GPIO pins in sleep state
I (283) sleep: Enable automatic switching of GPIO sleep configuration
I (291) main_task: Started on CPU0
I (301) main_task: Calling app_main()
Hello world!
This is esp32s3 chip with 2 CPU core(s), WiFi/BLE, silicon revision v0.2, 2MB external flash
Minimum free heap size: 386880 bytes
For the C3:

Code: Select all

I (24) boot: ESP-IDF v5.2 2nd stage bootloader
I (24) boot: compile time Mar  6 2024 08:18:08
I (25) boot: chip revision: v0.4
I (27) boot.esp32c3: SPI Speed      : 80MHz
I (32) boot.esp32c3: SPI Mode       : DIO
I (37) boot.esp32c3: SPI Flash Size : 2MB
I (41) boot: Enabling RNG early entropy source...
I (47) boot: Partition Table:
I (50) boot: ## Label            Usage          Type ST Offset   Length
I (58) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (65) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (73) boot:  2 factory          factory app      00 00 00010000 00100000
I (80) boot: End of partition table
I (84) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=09e18h ( 40472) map
I (99) esp_image: segment 1: paddr=00019e40 vaddr=3fc8ae00 size=0122ch (  4652) load
I (102) esp_image: segment 2: paddr=0001b074 vaddr=40380000 size=04fa4h ( 20388) load
I (113) esp_image: segment 3: paddr=00020020 vaddr=42000020 size=16e48h ( 93768) map
I (133) esp_image: segment 4: paddr=00036e70 vaddr=40384fa4 size=05d80h ( 23936) load
I (141) boot: Loaded app from partition at offset 0x10000
I (141) boot: Disabling RNG early entropy source...
I (153) cpu_start: Unicore app
I (161) cpu_start: Pro cpu start user code
I (161) cpu_start: cpu freq: 160000000 Hz
I (161) cpu_start: Application information:
I (164) cpu_start: Project name:     blink
I (169) cpu_start: App version:      1
I (174) cpu_start: Compile time:     Mar  6 2024 08:17:55
I (180) cpu_start: ELF file SHA256:  0c4d12fe4...
I (185) cpu_start: ESP-IDF:          v5.2
I (190) cpu_start: Min chip rev:     v0.3
I (194) cpu_start: Max chip rev:     v1.99 
I (199) cpu_start: Chip rev:         v0.4
I (204) heap_init: Initializing. RAM available for dynamic allocation:
I (211) heap_init: At 3FC8CFC0 len 00033040 (204 KiB): RAM
I (217) heap_init: At 3FCC0000 len 0001C710 (113 KiB): Retention RAM
I (224) heap_init: At 3FCDC710 len 00002950 (10 KiB): Retention RAM
I (231) heap_init: At 50000010 len 00001FD8 (7 KiB): RTCRAM
I (238) spi_flash: detected chip: generic
I (242) spi_flash: flash io: dio
W (246) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
I (260) sleep: Configure to isolate all GPIO pins in sleep state
I (266) sleep: Enable automatic switching of GPIO sleep configuration
I (273) main_task: Started on CPU0
I (273) main_task: Calling app_main()
Hello world!
This is esp32c3 chip with 1 CPU core(s), WiFi/BLE, silicon revision v0.4, 2MB external flash
Minimum free heap size: 327952 bytes

Now, as for the code I'm trying to do a simple i2c scan with:

Code: Select all

#include <stdio.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

// Latest docs from Espressif suggest this is how we import drivers for i2c devices. 
// https://docs.espressif.com/projects/esp-idf/en/v5.2/esp32/api-reference/peripherals/i2c.html
#include "driver/i2c_master.h"

#define I2C_MASTER_SCL_IO 9        /*!< GPIO number for I2C master clock */
#define I2C_MASTER_SDA_IO 10        /*!< GPIO number for I2C master data  */
#define I2C_MASTER_PORT I2C_NUM_0    /*!< I2C port number for master dev */
#define I2C_MASTER_FREQ_HZ 400000   /*!< I2C master clock frequency  - FAST MODE */


static void i2c_scan_task(void *arg) {


     // -------------------------
    // Configure i2c

    // Per these docs:
    // https://docs.espressif.com/projects/esp-idf/en/v5.2/esp32/api-reference/peripherals/i2c.html#i2c_master_controller
    // We are configuring the i2c master bus first.
    i2c_master_bus_config_t i2c_master_config = {
        .clk_source = I2C_CLK_SRC_DEFAULT,
        .i2c_port = I2C_MASTER_PORT,
        .scl_io_num = I2C_MASTER_SCL_IO,        // SCL pin
        .sda_io_num = I2C_MASTER_SDA_IO,        // SDA pin
        .glitch_ignore_cnt = 7,                 // a default from esp's docs
        .flags.enable_internal_pullup = true,
    };

    i2c_master_bus_handle_t bus_handle;
    i2c_new_master_bus(&i2c_master_config, &bus_handle);

    while (1) {
        
        printf("Scanning I2C bus...\n");

        for (uint8_t addr = 1; addr < 127; addr++) {

            uint8_t write_address = (addr << 1) | 0;
            uint8_t read_address = (addr << 1) | 1;

            esp_err_t error_status = i2c_master_probe(bus_handle, 
                                                      addr, 
                                                      -1);

            // If we received the ACK bit, we found something! Print its address.
            if (error_status == ESP_OK) {
                printf("Found device at address %d (0x%02X)\n", addr, addr);
                printf("Write address: %d (0x%02X)\n", write_address, write_address);
                printf("Read address: %d (0x%02X)\n", read_address, read_address);
                
            }

         }

        vTaskDelay(2000 / portTICK_PERIOD_MS); // Wait 2 seconds before rescanning.
    }


}


void app_main() {
    xTaskCreate(i2c_scan_task, "i2c_scan_task", 4096, NULL, tskIDLE_PRIORITY, NULL);
}
When I install and run this code on a C3, I see:

Code: Select all

Scanning I2C bus...
Found device at address 54 (0x36)
Write address: 108 (0x6C)
Read address: 109 (0x6D)
However, when I install and run it on my S3, I see:

Code: Select all

Scanning I2C bus...
Scanning I2C bus...
Scanning I2C bus...
Scanning I2C bus...
I've tried using different pins, but can't seem to produce a different result.

The S3 I'm using is:
https://www.amazon.com/dp/B0BYSB66S5?ps ... ct_details
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