ESP32 Forum

Hi,

The linker script "...../esp_rom/esp32/ld/esp32.rom.libgcc.ld" starts as follows:

[Codebox]
/* Unlike other ROM functions which are exported using PROVIDE, which declares
weak symbols, these libgcc functions are exported using assignment,
which declares strong symbols. This is done so that ROM functions are always
used instead of the ones provided by libgcc.a.
*/

__absvdi2 = 0x4006387c;
__absvsi2 = 0x40063868;
__adddf3 = 0x40002590;
__addsf3 = 0x400020e8;
__addvdi3 = 0x40002cbc;
__addvsi3 = 0x40002c98;
__ashldi3 = 0x4000c818;
__ashrdi3 = 0x4000c830;
__bswapdi2 = 0x40064b08;
__bswapsi2 = 0x40064ae0;
__clrsbdi2 = 0x40064b7c;
__clrsbsi2 = 0x40064b64;
__clzdi2 = 0x4000ca50;
__clzsi2 = 0x4000c7e8;
__cmpdi2 = 0x40063820;
__ctzdi2 = 0x4000ca64;
__ctzsi2 = 0x4000c7f0;
__divdc3 = 0x400645a4;
__divdf3 = 0x40002954;
__divdi3 = 0x4000ca84;
__divsi3 = 0x4000c7b8;
__eqdf2 = 0x400636a8;
__eqsf2 = 0x40063374;
__extendsfdf2 = 0x40002c34;
[/Codebox]

the problem is, according to the TRM, address region 0x4006_0000 to 0x4006_FFFF (64KB) is reserved. But addresses in this range are referenced above. How can this be? Is this region actually mapped to ROM?

It looks like that needs to be updated. As far as I can tell, we can think of IROM as one contiguous 448K block @ 0x40000000, the last 64K of which is also byte-addressable over the data bus at 0x3ff90000 as "ROM1" (ie. ROM1 == 0x3ff90000 == 0x40060000).

I'm aware of remapping... but I couldn't find anything in the TRM that mentions that ROM0 specifically is mappable to a reserved region in I-space. Could you please point me to the specific page/section? Perhaps this is mentioned in some source file instead?

Table 1-2, and section 1.3.2.1.

There is nothing about ROM1 addressing via the instruction bus @ 0x40060000, however. I've only deduced this by literally comparing the contents of memory at these addresses. Give it a try to confirm for yourself, if you like.

Knowing this, it's more intuitive to think of ROM as I've described in the previous comment imo