ESP32 Forum

I noticed ESP Privilege Separation project on github https://github.com/espressif/esp-privilege-separation which is very interesting.

Unfortunately it is in beta and does not seem to support recent idf releases such as v5.1.1, it requires idf patches and looking at the example sdkconfig.defaults https://github.com/espressif/esp-privil ... g.defaults it seems to disable the use of the second core and any hardware acceleration of sha/aes.

Are the single core mode and hw acceleration being disabled inherit requirements for the privilege separation mechanism?
Is support coming to recent idf releases?

I see the S3 has a ton of efuses, is it possible to have a hw only read efuse that the hardware can use to do aes or rsa or ecdsa but not allowed to be read by firmware?

is it possible to have a hw only read efuse that the hardware can use to do aes or rsa or ecdsa but not allowed to be read by firmware?

Apparently, only the Digital Signature and HMAC peripherals can use "read-protected" efuses.
As a work-around it's possible to use the HMAC to do key derivation for subsequent software cryptography. This however means that the actual key will be accessible to the firmware during crypto operations, but the underlying HMAC key cannot be read/copied from the chip. An attacker would need to extract the key from a running application, and if IVs/salts are used any potentially extracted key would only be valid for encryption or decryption of a single message.