ESP32 Forum

Posted: **Mon Sep 25, 2023 5:09 pm**

So we have an application originally developed using IDF 4.2 and I am in the process of uplifting to 5.1. So I encountered the usual trivial stuff that needed addressing, stricter compiler, obvious changes to structures and components etc.

I have resolved these with the exception of legacy ADC that needs some attention.

The problem I am having is that the board reboots after about 10s and I am not getting my startup messages I am expecting on the UART.

So the board starts and I get startup information that ends in:

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I (690) cpu_start: App version:      1.3.4
I (695) cpu_start: Compile time:     Sep 25 2023 17:44:21
I (701) cpu_start: ELF file SHA256:  7ccc72b40d9cd9eb...
I (707) cpu_start: ESP-IDF:          v5.1.1-439-gcb174b0fe1
I (713) cpu_start: Min chip rev:     v0.0
I (718) cpu_start: Max chip rev:     v3.99
I (723) cpu_start: Chip rev:         v1.0
I (728) heap_init: Initializing. RAM available for dynamic allocation:
I (735) heap_init: At 3FFAFF10 len 000000F0 (0 KiB): DRAM
I (741) heap_init: At 3FFB6388 len 00001C78 (7 KiB): DRAM
I (747) heap_init: At 3FFB9A20 len 00004108 (16 KiB): DRAM
I (753) heap_init: At 3FFCBEB0 len 00014150 (80 KiB): DRAM
I (759) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (765) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (772) heap_init: At 4009F8BC len 00000744 (1 KiB): IRAM
I (779) spi_flash: detected chip: gd
I (782) spi_flash: flash io: dio
W (786) ADC: legacy driver is deprecated, please migrate to `esp_adc/adc_oneshot.h`

I am expecting a message after this which gives me the reset reason from the following code:

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esp_reset_reason_t reason = esp_reset_reason();
ESP_LOGI(COMPONENT_NAME, "Reset reason: %d", (int) reason);
printf("Reset reason: %d", (int) reason);

So next step is to try and attach the debugger with the command

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idf,py openocd gdb

which gives output ending with:

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[esp32.cpu1] Target halted, PC=0x40000400, debug_reason=00000000
[esp32.cpu1] Reset cause (14) - (CPU1 reset by CPU0)
[esp32.cpu0] Reset cause (3) - (Software core reset)
Warning: 'flushregs', an alias for the command 'maintenance flush register-cache', is deprecated.
Use 'maintenance flush register-cache'.

Hardware assisted breakpoint 1 at 0x400d7aac: file /path_to_file/AppMain.cpp, line 111.

The system hangs here for a while and then after about 10 seconds the following is added to the output:

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[esp32.cpu0] Debug controller was reset.
[esp32.cpu0] Core was reset.
[esp32.cpu0] Target halted, PC=0x4000921A, debug_reason=00000000
[esp32.cpu0] Reset cause (16) - (RTC WDT core and rtc reset)

Just wondering is anyone has any tips on how I can work out what is going on as I can't event get a debugger attached to the system.

Thanks in advance,
Mark

ESP32 Forum

Board reboots after uplifting IDF from 4.2 to 5.1

Board reboots after uplifting IDF from 4.2 to 5.1