question about the clock of I2S
Posted: Fri Mar 10, 2023 8:04 am
I have some question about how the mclk is generated in I2S module. In esp32 technical reference manual, there have one session.
As is shown in Figure 12-2, I2Sn_CLK, as the master clock of I2S module, is derived from the 160 MHz clock PLL_D2_CLK or the configurable analog PLL output clock APLL_CLK. The serial clock (BCK) of the I2S module is derived from I2Sn_CLK. The I2S_CLKA_ENA bit of register I2S_CLKM_CONF_REG is used to select either PLL_D2_CLK or APLL_CLK as the clock source for I2Sn. PLL_D2_CLK is used as the clock source for I2Sn, by default.
and I found that every bclk will have four mclk.
this can this four mclk be changed and how to modify this mclk rate.
As is shown in Figure 12-2, I2Sn_CLK, as the master clock of I2S module, is derived from the 160 MHz clock PLL_D2_CLK or the configurable analog PLL output clock APLL_CLK. The serial clock (BCK) of the I2S module is derived from I2Sn_CLK. The I2S_CLKA_ENA bit of register I2S_CLKM_CONF_REG is used to select either PLL_D2_CLK or APLL_CLK as the clock source for I2Sn. PLL_D2_CLK is used as the clock source for I2Sn, by default.
and I found that every bclk will have four mclk.
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