ESP32 Forum

ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x5 (DSLEEP),boot:0x9 (SPI_FAST_FLASH_BOOT)
pro cpu reset by JTAG
SPIWP:0xee
mode:DIO, clock div:2
load:0x3fce3810,len:0x11a8
load:0x403c9700,len:0xa50
load:0x403cc700,len:0x2c30
SHA-256 comparison failed:
Calculated: 23129337a307384c585dc6bec46edfc4728e608ef452347a95342de138e91810
Expected: 09f8dda7b521a08b42186da7eb05525e96ba6b9b2e6872151b8a63c612bc11b9
Attempting to boot anyway...
entry 0x403c9894

[16:02:49.877]收←◆Not a ULP-RISC V wakeup (cause = 11)

[16:02:50.871]收←◆Entering deep sleep

Pretty sure ESP32-S3 is a Xtensa core and the ESP32-C3 is RISC-V.

The ULP in the S3 is a RiscV-based core, though.