Software reset (SW_RST) timeout of the EMAC?

[ThomasBit]

Hi

I have a ESP32 WROOM using my own board. Using a KSZ8081 PHY and external 50 MHz crystal.
I'm using GPIO0 as clock input. The oscillator is controlled with the RESET_N signal, so I dont accidentally starts the bootloader.
Al signals seens to work.
But the reset bit of the EMAC never get cleared (emac_ll_is_reset_done: dma_regs->dmabusmode.sw_rst)?
It is the SW_RST of the DMABUSMODE register.

I have:
CONFIG_ETH_RMII_CLK_INPUT=y
CONFIG_ETH_RMII_CLK_IN_GPIO = 0

and emac_hal_iomux_rmii_clk_input and emac_ll_clock_enable_rmii_input is run during initialization.

but emac_esp32_init still fail when the SW_RST bit is checked.

Only thing I can imagine is that the 50 MHz does not run, but the signal on the oscillator are ok. (But is difficult to measure the clock signal with an oscilloscope)

Using esp-idf version 4.4.1

Any suggestions where to look?

Best regards
Thomas

[ESP_ondrej]

Hi Thomas,

were you able to move forward with this issue? I saw you had different posts...

It really seems you have problems with RMII CLK but hard to say why. Could you please share schematics?

Why do you think it is difficult to measure the clock signal with an oscilloscope? The only reason I can imagine is you may have oscilloscope with lower bandwidth so the signal may not appear as square but you should be able to see something with 50 MHz period.

Thanks
Ondrej