SPI driver huge malfunction
Posted: Tue Dec 03, 2019 12:21 am
I struggle with a huge SPI driver malfunction:
Lets take DS1390 RTC (but some problems occurs with all devices I've tested).
Chip supports SPI in mode 1 or 3, up to 4MHz. After receiving address it replies with corresponding bytes of datetime.
Below there is a screen from logic analyzer:
As you can see:
- CLK mode is shifted,
- MOSI transmit some random bytes after command phase
- when higher frequencies (4MHz) CLK duty seems inconsistent
When I write similar program for arduino everything works.
Below I post logic analyzer screen for arduino program that shows how it should work (same configuration, same environment, same board):
Lets take DS1390 RTC (but some problems occurs with all devices I've tested).
Chip supports SPI in mode 1 or 3, up to 4MHz. After receiving address it replies with corresponding bytes of datetime.
Code: Select all
static void ds1390_spi_init() {
spi_bus_config_t buscfg = {
.miso_io_num=PIN_NUM_SPI_MISO, .mosi_io_num=PIN_NUM_SPI_MOSI, .sclk_io_num=PIN_NUM_SPI_CLK,
.quadwp_io_num=-1, .quadhd_io_num=-1,
.max_transfer_sz=32 // Does it take address and command bits?
};
spi_device_interface_config_t devcfg = {
.spics_io_num=PIN_NUM_SPI_RTC_CS,
.clock_speed_hz=40000, // 4kHz used, 4MHz max
.mode=1, // SPI MODE 1
.command_bits=8, // 8-bit command length
.queue_size=1
};
spi_bus_initialize(VSPI_HOST, &buscfg, 1 /*dma_chan - 0 no DMA*/);
ESP_ERROR_CHECK(spi_bus_add_device(VSPI_HOST, &devcfg, &ds1390_spi));
}
Code: Select all
void ds1390_get_time() {
char * buffer = heap_caps_malloc(8, MALLOC_CAP_DMA);
spi_transaction_t transaction;
memset(&transaction, 0, sizeof(transaction));
transaction.cmd = DS1390_REG_SECONDS;
transaction.rx_buffer = buffer;
transaction.length = 8 * 8;
assert(spi_device_polling_transmit(ds1390_spi, &transaction) == ESP_OK);
ESP_LOGI(TAG, "DS1390 Time: %02x %02x %02x %02x %02x %02x %02x %02x", buffer[0], buffer[1], buffer[2], buffer[3], buffer[4], buffer[5], buffer[6], buffer[7]);
free(buffer);
}
As you can see:
- CLK mode is shifted,
- MOSI transmit some random bytes after command phase
- when higher frequencies (4MHz) CLK duty seems inconsistent
When I write similar program for arduino everything works.
Below I post logic analyzer screen for arduino program that shows how it should work (same configuration, same environment, same board):