Support for Serial Management Interface (SMI)
Posted: Thu Oct 31, 2019 2:39 pm
Hi,
The ethernet switch KSZ8863RLL(http://ww1.microchip.com/downloads/en/D ... 02335B.pdf) requires a non standard SMI interface to have full access to all control/status registers. This differs from the standard MDIO interface supported by ESP32 by 2 parameters: the Read/Write OP Code and PHY Address fields in the frame format, as shown in tables 3-8 and 3-9 in the switch datasheet on page 24.
I need to be able to set the OP Code to 00 and bit 4 of the PHY address to 0 or 1 (R/W). I have tried modifying the write function
so that it meets these requirements, but I am unable to do so.
I am not sure what value I need to write into the register on line
I have tried playing around with the values 0x3 and ((0x3) << 2), which seem to decide whether the operation is read or write but I cannot change the OP Code to 00 in any way.
Can this be done somehow or is it not supported at all?
The ethernet switch KSZ8863RLL(http://ww1.microchip.com/downloads/en/D ... 02335B.pdf) requires a non standard SMI interface to have full access to all control/status registers. This differs from the standard MDIO interface supported by ESP32 by 2 parameters: the Read/Write OP Code and PHY Address fields in the frame format, as shown in tables 3-8 and 3-9 in the switch datasheet on page 24.
I need to be able to set the OP Code to 00 and bit 4 of the PHY address to 0 or 1 (R/W). I have tried modifying the write function
Code: Select all
void esp_eth_smi_write(uint32_t reg_num, uint16_t value)
{
uint32_t phy_num = emac_config.phy_addr;
while (REG_GET_BIT(EMAC_GMIIADDR_REG, EMAC_MIIBUSY) == 1) {
}
REG_WRITE(EMAC_MIIDATA_REG, value);
REG_WRITE(EMAC_GMIIADDR_REG, 0x3 | ((reg_num & 0x1f) << 6) | ((phy_num & 0x1f) << 11) | ((0x3) << 2));
while (REG_GET_BIT(EMAC_GMIIADDR_REG, EMAC_MIIBUSY) == 1) {
}
}
I am not sure what value I need to write into the
Code: Select all
EMAC_GMIIADDR_REG
Code: Select all
REG_WRITE(EMAC_GMIIADDR_REG, 0x3 | ((reg_num & 0x1f) << 6) | ((phy_num & 0x1f) << 11) | ((0x3) << 2));
Can this be done somehow or is it not supported at all?