Page 1 of 1

Lack of understanding UART Pattern post_idle time

Posted: Fri Jun 21, 2019 10:04 am
by gost.404
Hi everyone.

I have a confusing situation: I'm trying to set up UART Pattern interrupt but the observed result is different than I expect.
I configure UART to 921600 baud rate 8N1. From the documentation I read next:
post_idle: idle time after the last pattern character, 24bit value, unit is APB (80Mhz) clock cycle. When the duration is less than this value, it will not take the previous data as the last at_cmd char

In my case, post_idle should be equal to 1 byte:

Code: Select all

 post_idle = f_apb / (baud / bits_per_byte) * bytes_qty = 80 000 000 / (921 600 * 10) = 868
And it works, but when I decide to decrease post_idle to ~800 I expect that UART will receive two separate events and it doesn't!
I got expected behavior only with post_idle = ~300.

So my question: What are the start and stop points for measuring post_idle interval?

Re: Lack of understanding UART Pattern post_idle time

Posted: Sat Jun 22, 2019 5:17 pm
by WiFive
What is the spacing between the two chars?

Re: Lack of understanding UART Pattern post_idle time

Posted: Mon Jun 24, 2019 1:01 pm
by gost.404
Sorry, I don't understand the question.

Re: Lack of understanding UART Pattern post_idle time

Posted: Mon Jun 24, 2019 4:55 pm
by WiFive
You said you are expecting two events, which two? What are you sending? CHAR idle CHAR? I would guess the idle time is measured from the rising edge of the stop bit to the falling edge of the next start bit.

Re: Lack of understanding UART Pattern post_idle time

Posted: Tue Jun 25, 2019 10:46 am
by gost.404
OK, I got.
In my test, I send next string:

Code: Select all

"Test\nx\n"
For communication with ESP32, I use PC with USB-UART adapter. Test string is sent without interrupts in one message.

UART pattern configured in next way:

Code: Select all

uart_enable_pattern_det_intr(UART_PORT_NUM, '\n', 1, 10000, 10, 300);
I would guess the idle time is measured from the rising edge of the stop bit to the falling edge of the next start bit.
This is one of my assumptions, but I can't find any information in the Technical Reference Manual.

Re: Lack of understanding UART Pattern post_idle time

Posted: Wed Jun 26, 2019 12:50 am
by WiFive
300 works at 115200 so it could be somewhere ~½bit. That would imply it starts at the bit sampling time of the stop bit and ends at the falling edge of the start bit.

when you set pre-idle < ½bit, post-idle > ½bit, timeout < ½bit (+ is cmd char)
+x not detected
x+ detected
x+x+ last char detected
++x++ not detected ??

when you set pre-idle > ½bit, post-idle < ½bit, timeout < ½bit (+ is cmd char)
+x detected
x+ not detected
x+x+ not detected
++x++ first char detected

when you set pre-idle < ½bit, post-idle < ½bit, timeout < ½bit (+ is cmd char)
+x detected
x+ detected
x+x+ both detected
++x++ all detected

Re: Lack of understanding UART Pattern post_idle time

Posted: Thu Jun 27, 2019 5:32 pm
by WiFive
Anyone can explain why?

++x++ not detected ??
++x++ first char detected
++x++ all detected