ESP_Sprite wrote:For what it's worth - while we don't have a timeline for it, we also have the idea to add non-flash-cache-based psram access to esp-idf. This would mean that you can fetch data from the psram or write data to psram using a function call, but you cannot directly allocate memory pointers in it or store variables in it. While it won't suffice for all applications, for example audio applications can benefit from it. Because the issues are purely in the cache, this way of accessing it will also be compatible with v0 ESP32s.
ok Jeroen. honest thank you for your effort - i understand now better the things in background.
so i talked to wear leveling and other too in the past - ...
this non-flash-cache-based psram access would help - cause i can not wait - ( you know me )
i try this in the past - but have no access -
i know - we must put all function to the non cache - to IRAM -
one thing i do not understand, perhabs you can help in this way with an Info about,
i know - you are very detailed and
you are visionaer - so i ask you for hope to get answers:
in the technical reference there is a picture, that psram share CLK with flash
you know.
we know now, that this picture must be wrong, cause
CLK need to separate for psram. and
here comes the same confirm
- at first, can you confirm, the picture is wrong?
- does this mean, that only the workaround need this for rev1 or is this gerenally for the psram then?
we know now, that the pins on this picture must be wrong then too ?! ,
cause the pic shows DI, DO, WP and HOLD
QIO mode
but in the pSRAM support, we use DI, DO and WP ( mode ? )
this is a diffenet mode -
hold is not named and not use.
i ask for the mode, cause we have 1 bit Input and Output separate or 4 bit I/O common interface
1 bit Input and Output separate means DI, DO right?
and
4 bit I/O common interface means SD_0..SD_3, right?
- psram_all.jpg (78.9 KiB) Viewed 17203 times
btw XTX sales espressif brandmarked pSRAM - so i think - it is the same
from the future/psram-maloc
To connect the ESP-PSRAM chip to the ESP32, connect the following signals:
- PSRAM /CE (pin 1) - ESP32 GPIO 17
PSRAM SO (pin 2) - flash DO
PSRAM SIO[2] (pin 3) - flash WP
PSRAM SI (pin 5) - flash DI
PSRAM SCLK (pin 6) - ESP32 GPIO 16
PSRAM Vcc (pin 8) - ESP32 VCC_SDIO
in which mode the pSRAM then comes to rev1 in this ?
and which mode you would use for the non-flash-cache-based psram access then?
honest honest honest - it is very sad that we got the wrover without an info from espressif ( they knowed that we need psram, cause we bought psram too to the wrovers in same package and ESP32-D2WDQ5 - ) that this wrover are rev0.
i do not believe, that they have this not knowed.
i wished, that here espressif goes opener to the companies for this - I have to digest this sad truth..
and contacted john and stanza with pleased now - for fast sending this beta rev1 wrover that we can work on psram here.
we have no possible way for use/test/show psram on esp32 - this is very sad after 3 years on espressif's products
but this is an other theme.
i know - you gave the tip to can mount wrover to the wrover kits - and that the espressif team do this too.
but what sense make this - if we can not use psram on the modules? -
here i missed the info "
but you can't use psram cause this is rev0"
this theme that rev0 does not support psram in this way - is
longer knowed in espressif - so i do not understand this tactic.
then we can save time and nerve and we professionals do not need to "Argue about ignorance"
now
wrover kit's are back - does this again be wroom-32 rev0 and do not support psram? or are this wrover modules with rev0 and this are not support psram or are this the versions with wrover rev1 ( beta ) ?
i ask cause
here the same - wrovers in the spot - with wrover modul and camera connector update, does this be wrover rev1 or again wrover rev0 and do not support psram
It looks very confusing -
"I found out ESP32 WROVER KIT，With SRAM Module"
can we use SRAM on it?
hope you understand me now better.
best wishes
rudi
ps:
now its clearing, psram 1.8, flash 1.8, CLK and CS in the VSDIO domain, and CLK must be separate.
now we need a code sceleton for using this pSRAM as usually SPI RAM Jeroen,
is this possible to test this on this way in a short time ( 1-2 days )
and do the same thing for a test ->
can you help? can you provide a code example to huck up the pSRAM on wrover rev0 SoC'S ?
if i can use the pSRAM on this way for pushing data and read data
this helps - we need not the cache maloc version in this step
( later sure - we need this - but then better wait and use "ESP64" instead ESP32 rev1 with workarounds )
Code: Select all
int ICACHE_FLASH_ATTR spiRamTest() {
int x;
int err=0;
char a[64];
char b[64];
char aa, bb;
for (x=0; x<64; x++) {
a[x]=x^(x<<2);
b[x]=0xaa^x;
}
spiRamWrite(0x0, a, 64);
spiRamWrite(0x100, b, 64);
spiRamRead(0x0, a, 64);
spiRamRead(0x100, b, 64);
for (x=0; x<64; x++) {
aa=x^(x<<2);
bb=0xaa^x;
if (aa!=a[x]) {
err=1;
// printf("aa: 0x%x != 0x%x\n", aa, a[x]);
}
if (bb!=b[x]) {
err=1;
// printf("bb: 0x%x != 0x%x\n", bb, b[x]);
}
}
return !err;
}
