I have some code that requires low interrupt jitter. Even with level-5 interrupt jitter still exists, and the jitter can be 23 CPU cycles caused by some uncontrollable WiFi task. To reduce the jitter, I set the timer 100 CPU cycles earlier than the objective time, then delay the commands in the handler until the real objective time arrives. (The same concept can be found in some STM32 chips to reduce/avoid jitter by introducing some delay)
In the interrupt handler, I compare the ccount with the objective time in a loop until the objective time is current. However, each iteration of the loop takes 7 CPU cycles, which limits the accuracy of the delay. I'm wondering if there is any other command or workaround to further improve the accuracy.
An example of the logic is shown below. command 'rsr' takes 1 cpu cycle, and branch command 'blt' takes 6 CPU cycles. When the aforementioned uncontrollable WiFi task run, one iteration of the loop could take up to 12 CPU cycles. Is that normal?
Code: Select all
//level-5 interrupt handler
movi a6, 100 //The objective time
LoopDelay:
rsr a5, ccount
blt a5, a6, LoopDelay //if current time < timer setting, loop back to wait.
//other commands that require low jitter.
//......
Best,
Wayne