UART_BUFFER_FULL and UART_FIFO_OVF difference

[gd_code]

Hi all,

I am confused about the two events UART_BUFFER_FULL and UART_FIFO_OVF. What is the exact difference between these two events: what do they represent, when do they occur and especially to which RX buffer do they apply?

The documentation on UART (https://docs.espressif.com/projects/esp ... /uart.html) isn't really helping, as the use of the terminology RX ring buffer and RX FIFO is very confusing to me in the docs. As far as I understand (when also reading the technical document), there is a RX FIFO hardware buffer (128 bytes size?) and there is the RX (FIFO) ring buffer (which you install using `uart_driver_install()`). It is unclear to me which RX buffer is referred to in different parts of the documentation. Some examples:
* In this part (https://docs.espressif.com/projects/esp ... munication), I guess it is about the RX HW FIFO buffer and not the ring buffer, because when I look at the UART structure in the technical document, the UART FSM feeds into the RX HW FIFO (https://www.espressif.com/sites/default ... ual_en.pdf)
* In the `uart_read_bytes()` part (https://docs.espressif.com/projects/esp ... TickType_t), it says RX FIFO buffer, but here I guess it is about the ring buffer because they also refer to `uart_flush()` which should clear the RX ring buffer as I can read further down in the documentation.

The confusion about these RX FIFO and RX ring buffer in the documentation adds to my confusion about the UART_BUFFER_FULL and UART_FIFO_OVF events.

Kind regards,
gd_code

[WiFive]

The hardware fifo receives the bytes and then they are copied into the ring buffer in ram when the threshold is reached or at end of frame. If the hardware fifo overflows before the bytes can be copied out you get UART_FIFO_OVF. If the bytes can't be copied into the ring buffer because it is full you get UART_BUFFER_FULL.

[gd_code]

Thanks for the clear answer!