High Level Interrupt on external GPIO Interrupt

opcode_x64
Posts: 47
Joined: Sun Jan 13, 2019 5:39 pm

Re: High Level Interrupt on external GPIO Interrupt

Postby opcode_x64 » Tue Jan 22, 2019 11:07 am

@ESP_Sprite:

No, I mean GPIO_NUM_15, because my interrupt is configured to GPIO_NUM_4. I am using GPIO_NUM_15 just to generate a test signal, so I can measure with my digital oscilloscope "easily" the latency of the interrupt raise time.

GPIO configuration:
External Interrupt on Pin: GPIO_NUM_4
Test Signal Output on Pin: GPIO_NUM_15


Program flow
  1. External Signal on GPIO_NUM_4 triggers the interrupt
  2. Program jumps to interrupt handler (xt_highint5)
  3. In xt_highint5: Program make GPIO_NUM_15 to HIGH
  4. In xt_highint5: Program clears the interrupt status of GPIO_NUM_4 (!!)
  5. Programm returns from interrupt but crashes with "Core 0 panic'ed (Unhandled Debug Exception")
Best regards,
opcode_x64

opcode_x64
Posts: 47
Joined: Sun Jan 13, 2019 5:39 pm

Re: High Level Interrupt on external GPIO Interrupt

Postby opcode_x64 » Tue Jan 22, 2019 12:13 pm

@ESP_Sprite

Sorry ! I read wrong your last posting... Of course you are right ! It has to be the register a15 ! It was a bit to late this night... sorry for that stupid mistake.

Please ignore my last posting...

Update:
Ok now it seems to work better... the ESP is not crashing, but it seems that the interrupt is raising twice...

I just generate a trigger signal and setting the GPIO_NUM_15 to HIGH and LOW. On my oscilloscope i can see two impulses of GPIP_NUM_15 instead of one. When I enter the interrupt handler, I am clearing the interrupt pin in STATUS_W1TC_REG firstly.

Here is my updated assembly interrupt handler code:

Code: Select all

.section .iram1,"ax"
 .global     xt_highint5
 .type       xt_highint5,@function
 .align      4
 .literal .GPIO_STATUS_W1TC_REG, 0x3FF4404C
 .literal .GPIO_OUT_W1TS_REG, 0x3FF44008
 .literal .GPIO_OUT_W1TC_REG, 0x3FF4400C
 .literal .GPIO__NUM_15, (1<<15)
 .literal .GPIO__NUM_4,  (1<<4)
xt_highint5:
/* clearing the interrupt status of GPIO_NUM_4 */
l32r a14, .GPIO_STATUS_W1TC_REG
l32r a15, .GPIO__NUM_4
s32i a15, a14, 0

/* setting GPIO_NUM_15 on high */
l32r a14, .GPIO_OUT_W1TS_REG
l32r a15, .GPIO__NUM_15
s32i a15, a14, 0

/* setting GPIO_NUM_15 on low */
l32r a14, .GPIO_OUT_W1TC_REG
l32r a15, .GPIO__NUM_15
s32i a15, a14, 0

rsr     a0, EXCSAVE_5
rfi     5

ESP_Sprite
Posts: 9719
Joined: Thu Nov 26, 2015 4:08 am

Re: High Level Interrupt on external GPIO Interrupt

Postby ESP_Sprite » Wed Jan 23, 2019 2:31 am

Before the two last lines that return from the interrupt, can you try adding this?

Code: Select all

l32r a14, .GPIO_STATUS_REG
l32i a14, a14, 0
memw
The idea is that the interrupt acknowledge may be 'stuck' in a load/store unit of the CPU or somewhere in a peripheral, and hasn't properly executed yet before the interrupt returns, causing it to trigger a 2nd time. These three lines force the write to complete. (Note that either the top 2 lines or the memw by itself may also work, I'm not quite sure and don't have the setup to try it here.)

opcode_x64
Posts: 47
Joined: Sun Jan 13, 2019 5:39 pm

Re: High Level Interrupt on external GPIO Interrupt

Postby opcode_x64 » Wed Feb 13, 2019 6:43 am

Hello ESP_Sprite,

sorry for my very late reply. I was very busy in the last weeks (was moving with my wife and daughter to a new flat, work etc...) and so I could not try your last solution/hint. I hope you are doing well. I will just try your last solution/hint as soon as possible.

Best regards,
opcode_x64

filzek
Posts: 5
Joined: Tue Jul 10, 2018 8:27 pm

Re: High Level Interrupt on external GPIO Interrupt

Postby filzek » Thu Jun 20, 2019 2:46 am

ESP_Sprite wrote:
Wed Jan 23, 2019 2:31 am
Before the two last lines that return from the interrupt, can you try adding this?

Code: Select all

l32r a14, .GPIO_STATUS_REG
l32i a14, a14, 0
memw
The idea is that the interrupt acknowledge may be 'stuck' in a load/store unit of the CPU or somewhere in a peripheral, and hasn't properly executed yet before the interrupt returns, causing it to trigger a 2nd time. These three lines force the write to complete. (Note that either the top 2 lines or the memw by itself may also work, I'm not quite sure and don't have the setup to try it here.)

@ESP_Sprite

The basic idea is to create a scenario where:

GPIO 21 is attached to a non-shared interrupt running C code.

HWTIMER0_0 with a non-shared interrupt running assembly to enable a GPIO 4
HWTIMER0_1 with a non-shared interrupt running assembly to enable a GPIO 5
HWTIMER1_0 with a non-shared interrupt running assembly to disable GPIO 4 and GPIO 5

Major problem is that ESP32 in DEV 4.0 cant run well in ISR from external in GPIO with WIFI in concurrent mode, so, we think run it exclusive ISR alloc shall solve the problem, what do you think?

ESP_Sprite
Posts: 9719
Joined: Thu Nov 26, 2015 4:08 am

Re: High Level Interrupt on external GPIO Interrupt

Postby ESP_Sprite » Thu Jun 20, 2019 4:55 am

Filzek: Sorry, I have no idea what you're on about. Perhaps you want to start a new topic for this, with a bit more information?

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