Esp32S3 : Interrupt Handling

[ThomasESP32]

Good morning,

I have a question concerning interrupt handling on Esp32S3 chip.
I am working on a firmware where is use drivers in order to start different peripherals.

I did not worry on interrupt allocation so far, but I have just added the UART driver and I get
an I2C interrupt allocation error when starting the firmware...

I do not know what are the CPUs interrupt vector used exactly, I just can say that only one task is running on CPU1
and the others are running on CPU0 (So, there are chances that all the CPU0 interrupt vectors are defined/used).

Are there methods that can be called in order to describe the CPU0 interrupt vector used ??
How can I do that ? The goal would be to have a map of the CPU0 interrupt vector used in order to understand what happen.

However, I have added the flag ESP_INTR_FLAG_SHARED when starting the I2C driver and when starting the UART driver and it seams that the I2C allocation error has desappeard.
The thing is that I do not know exactly what this flag does... Has I understand, it seams that many CPU0 interrupt vectors can be shared between many peripheral sources ?? Is it what it does ?
Does it works well ??? Because at the moment I do not know is my firmware (And more precisely the UART and I2C peripherals) work normally. Could you tell me ?


Thank you for your help on the subject,
best regards,

Thomas TRUILHE

[ThomasESP32]

Good afternoon,

I have printed the interrupt tables for CPU0 and CPU1, and I don't understand
why I get the interrupt allocation error because the tables are not full.

Moreover, with the SHARED flag, the UART peripheral int and the I2C peripheral int are on
the same vector but the UART does not manage to display the debut frame after some seconds...
Could you help ??

CPU 0 interrupt table :
0 : Peripheral, Level-Triggered : Prio 1 : 0
1 : Peripheral, Level-Triggered : Prio 1 : 0
2 : Peripheral, Level-Triggered : Prio 1 : 39 (RTC_CORE)
3 : Peripheral, Level-Triggered : Prio 1 : 59 (SYSTEM_TIMER_TARGET2)
4 : Peripheral, Level-Triggered : Prio 1 : 0
5 : Peripheral, Level-Triggered : Prio 1 : 8 (RWBLE)
6 : Internal/Timer0 : Prio 1 : Full
7 : Internal/Software : Prio 1 : 0
8 : Peripheral, Level-Triggered : Prio 1 : 5 (BT_BB)
9 : Peripheral, Level-Triggered : Prio 1 : 79 (CPU_INTR_CPU0)
10 : Peripheral, Level-Triggered : Prio 1 : 0
11 : Internal - Profiling : Prio 3 : 0
12 : Peripheral, Level-Triggered : Prio 1 : 52 (TG_WDT)
13 : Peripheral, Level-Triggered : Prio 1 : 0
14 : Periph : NMI : Prio NMI : 0
15 : Internal Timer 1 : Prio 3 : 0
16 : Internal Timer 2 : Prio 5 : 0
17 : Peripheral, Level-Triggered : Prio 1 : 28 (UART1), 40 (RMT), 42 (I2C)
18 : Peripheral, Level-Triggered : Prio 1 : 96 (USB)
19 : Peripheral, Level-Triggered : Prio 2 :67 (DMA_INT_CH1)
20 : Peripheral, Level-Triggered : Prio 2 : 0
21 : Peripheral, Level-Triggered : Prio 2 : 0
22 : Peripheral, Level-Triggered : Prio 3 : 0
23 : Peripheral, Level-Triggered : Prio 3 : 52 (TG_WDT)
24 : Peripheral, Level-Triggered : Prio 4 : 55 (TG1_WDT)
25 : Peripheral, Level-Triggered : Prio 4 : 56 (CACHE_IA), 85 (CORE_IRAM0), 86 (CORE_DRAM0), 87 ( CORE0_PIF), 94 (CACHE_CORE0)
26 : Peripheral, Level-Triggered : Prio 5 : 0
27 : Peripheral, Level-Triggered : Prio 3 : 0
28 : Peripheral, Level-Triggered : Prio 4 : 81 (CPU_INTR_FROM_CPU0)
29 : Internal Software : Prio 3 : 0
30 : Peripheral, Level-Triggered : Prio 4 : 0
31 : Peripheral, Level-Triggered : Prio 5 : 0

CPU 1 interrupt table :
0 : Peripheral, Level-Triggered : Prio 1 : 0
1 : Peripheral, Level-Triggered : Prio 1 : 0
2 : Peripheral, Level-Triggered : Prio 1 : 80 (CPU_INTR_CPU_1)
3 : Peripheral, Level-Triggered : Prio 1 : 72 (DMA_OUT_CH1_INT)
4 : Peripheral, Level-Triggered : Prio 1 : 0
5 : Peripheral, Level-Triggered : Prio 1 : 0
6 : Internal/Timer0 : Prio 1 : Full
7 : Internal/Software : Prio 1 : 0
8 : Peripheral, Level-Triggered : Prio 1 : 0
9 : Peripheral, Level-Triggered : Prio 1 : 0
10 : Peripheral, Level-Triggered : Prio 1 : 0
11 : Internal - Profiling : Prio 3 : 0
12 : Peripheral, Level-Triggered : Prio 1 : 0
13 : Peripheral, Level-Triggered : Prio 1 : 0
14 : Periph : NMI : Prio NMI : 0
15 : Internal Timer 1 : Prio 3 : 0
16 : Internal Timer 2 : Prio 5 : 0
17 : Peripheral, Level-Triggered : Prio 1 : 0
18 : Peripheral, Level-Triggered : Prio 1 : 0
19 : Peripheral, Level-Triggered : Prio 2 :0
20 : Peripheral, Level-Triggered : Prio 2 : 0
21 : Peripheral, Level-Triggered : Prio 2 : 0
22 : Peripheral, Level-Triggered : Prio 3 : 0
23 : Peripheral, Level-Triggered : Prio 3 : 58 (SYSTIMER_TARGET1)
24 : Peripheral, Level-Triggered : Prio 4 : 55 (TG1_WDT)
25 : Peripheral, Level-Triggered : Prio 4 : 56 (CACHE_IA), 89 (CORE1_IRAM0), 90 (CORE1_DRAM0), 91 (CORE1_PIF), 95 (CACHE_CORE_1)
26 : Peripheral, Level-Triggered : Prio 5 : 0
27 : Peripheral, Level-Triggered : Prio 3 : 0
28 : Peripheral, Level-Triggered : Prio 4 : 82 (CPU_INTR_FROM_CPU3)
29 : Internal Software : Prio 3 : 0
30 : Peripheral, Level-Triggered : Prio 4 : 0
31 : Peripheral, Level-Triggered : Prio 5 : 0


Is there a way to choose manually on which vector I want to put the peripheral interrupt vector ??
For example, the only methods that I execute in order to start the UART are :

Err = uart_driver_install(UART_PROD_PORT_NUM, UART_PROD_BUFFER_SIZE * 2, 0, 0, NULL, ESP_INTR_FLAG_SHARED);
Err = uart_param_config(UART_PROD_PORT_NUM, &uart_config);
Err = uart_set_pin(UART_PROD_PORT_NUM, UART_PROD_TX_PIN, UART_PROD_RX_PIN, UART_PROD_UNUSED_PIN,

are I don't see how to set the interrupt vector ....
the same thing for the other peripherals....

I have the possibility to choose the vector manually using the interrupt registers but I hope the driver methods
can do it automatically.

Thank you for your help,

Thomas TRUILHE