Explanation on ESP32 DevitKitV1 circuitry

[sunbear]

Can someone explain the attached circuitry to me? It is extracted from DOIT ESP32 DevKitV1 circuitry https://www.dropbox.com/s/jefwxxtufgwg0 ... s.pdf?dl=0.

After switching on this device, I know that both RTS and DTR are high, and this will lead to EN=GPIO0=3.3V to be true. When RTS is made low, I understand that EN will be low, i.e. 0V. When DTR is made low, I understand that GPIO0 will be low, i.e. 0V. Why is this the case? I dont' understand the purpose of directing the BJT emitter current to the DTR and to the base of the BJT at the DTR line. I also don't understand the purpose of then directing DTR BJT emitter current to the RTS and to the base of the BJT at the RTS line.

Appreciate if someone can help me understand the working of that figure of 8 circuitry loop. Thank you.

I was thinking that to switch on the BJT at the GPIO0 side, the base current of that BJT needs both RTS current + emitter current from the BJT at the EN side. To switch on the BJT at the EN side, the base current of that BJT needs both DTR current + emitter current from the BJT at the GPIO0 side. So when DTR=low=0V, emitter current from the EN side BJT become zero, and that will shut down the BJT at the GPIO0 side. But if that happens, how does the GPIO0 line voltage becomes zero? Also when the BJT at the EN side switches off, would not EN=0V? I am a bit confuse on how things work here.

[ESP_Stone]

As you know, we may have caps on EN or GPIO0, so there would have a slow rising edge on such signals. I suggest you can use a oscilloscope to have a test which would help you understand this a lot.

[bobtidey]

When either DTR,RTS are both high or both low then EN and GPIO0 will both be high. It is done this way to ensure that the chip will run normally under either of these conditions.

When DTR is high and RTS is low then GPIO0 is high and EN is low.

Similarly when RTS is high and DTR is low then EN is high and GPIO0 is low.

This does mean that it is not possible to pulse the EN signal while GPIO0 is low, but the programing sequence is to pulse EN low and then immediately set GPIO0 low.

On the ESP8266 the state of GPIO0 is read a short while after the EN returns high and so by then the GPIO0 is low for it to enter flash mode.

On the ESP32 the state of GPIO0 is read a bit quicker so it is possible that the sequence hasn't set GPIO0 low by then. This is why the ESP32 recommended circuit has an additional 1nF capacitor on the EN line. With a 10K pull up this gives about 10uSec further delay on the boot sequence starting up and gives more time to get the GPIO0 state low before it is read.