ESP32 Forum

Posted: **Sun Dec 15, 2024 12:14 am**

I want to have two synchronized (bit and frame) I2S output streams on an ESP32. I've read that this can be done by making one the master and the other the slave, and connecting the BCLK and WS pins externally. Of course it would be ideal to avoid using two pairs of pins and instead reuse the pins. Would it be possible to configure the GPIO matrix in a way that the slave peripheral uses the same BCLK and WS pins as the master peripheral?

Posted: **Tue Dec 17, 2024 1:21 pm**

Yes, I tried this. The data doesn't start at the same time, is the only issue. But you can connect the signals internally in the matrix:

Include esp_rom_gpio.h and hal/i2s_hal.h

Code: Select all

/* Connnect BCLK signal to GPIO4  */
esp_rom_gpio_connect_out_signal(GPIO_NUM_4, i2s_periph_signal[0].m_tx_bck_sig, 0, 0);
esp_rom_gpio_connect_in_signal(GPIO_NUM_4, i2s_periph_signal[1].s_rx_bck_sig, 0);
/* Connect WS signal to GPIO5 */
esp_rom_gpio_connect_out_signal(GPIO_NUM_5, i2s_periph_signal[0].m_tx_ws_sig, 0, 0);
esp_rom_gpio_connect_in_signal(GPIO_NUM_5, i2s_periph_signal[1].s_rx_ws_sig, 0);

Substitute your GPIO numbers. This is assuming I2S 0 is master.. Hat tip to L-KAYA on the github

Posted: **Wed Dec 18, 2024 6:21 pm**

Thank you for your post.

thefury wrote: ↑
Tue Dec 17, 2024 1:21 pm
The data doesn't start at the same time, is the only issue.

What's the delay? One sample?

Posted: **Tue Dec 24, 2024 2:59 pm**

Now that I looked at the logic analyzer screenshots it seems that there isn't a sample delay but just a slight phase delay. The data output still happens before the BCLK rising edge.

ESP32 Forum

Share clock pins between two I2S peripherals (master and slave)

Share clock pins between two I2S peripherals (master and slave)

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Re: Share clock pins between two I2S peripherals (master and slave)

Re: Share clock pins between two I2S peripherals (master and slave)