ESP32 Forum

Hi,
after checking schematics of WROOM32(ESP32/S seems to be the same), 6 pins SD0 - SD3, CMD and CLK (GPIO8 - GPIO11) are used as datalink between on-board flash and ESP32. They are also exposed as external pins on a board. What is actual purpose of this exposed pins? Is there any option to limit flash access from Q-SPI to D-SPI as startup configuration and leave UART1 TX/RX pins (SD2, SD3) available for external communication?

Hi frenkR,

Unfortunately, some of the pin uses at the SPI flash end make this a little difficult. SD2 is otherwise WP# on the SPI flash, and this pin is not used unless you configure the SPI flash to use it. So you can probably reuse that pin if you compile the firmware in DIO mode. However SD3 is HOLD# and this pin is used as HOLD# by default if quad SPI mode is disabled, so you probably can't drive it independently.

However, don't forget that the GPIO Matrix allows you to remap any pin function to any pin. So UART1 can be moved to any pins you like, you don't have to use the pins specified in the IOMUX list! (The only exception is if you need to use UART1 during the ROM bootloader phase, or if you need sub-25nanosecond latency or a >40Mbit UART data rate!)

Angus

hi,
that is perfect addition to Neil's hint about pin mapping and fits into . Now it is much more clear. Thank you.