Correct address for EFUSE_RD_REPEAT_ERR4_REG?
Posted: Thu Mar 09, 2023 6:52 am
It seems to be some inconsistency for the address of EFUSE_RD_REPEAT_ERR4_REG for the various ESP-* chips.
For example, for ESP32-S3, the TRM lists EFUSE_RD_REPEAT_ERR4_REG to be at offset 0x0190 in the Register Summary table.
When going to the details for EFUSE_RD_REPEAT_ERR4_REG however in the same TRM, it says it is at offset 0x018C.
The mem_definitions.py in esptool and the soc header files in esp-idf seem to use offset 0x018C.
Similar inconsistency applies for ESP32-S2, ESP-C3 and ESP32-C6 too.
Which address is correct? Please fix the documents/code to be consistent.
For example, for ESP32-S3, the TRM lists EFUSE_RD_REPEAT_ERR4_REG to be at offset 0x0190 in the Register Summary table.
When going to the details for EFUSE_RD_REPEAT_ERR4_REG however in the same TRM, it says it is at offset 0x018C.
The mem_definitions.py in esptool and the soc header files in esp-idf seem to use offset 0x018C.
Similar inconsistency applies for ESP32-S2, ESP-C3 and ESP32-C6 too.
Which address is correct? Please fix the documents/code to be consistent.