CAN controller clock and slow CAN bitrates

[hwmaier]

Hi all,

The ESP32 CAN controller is clocked with APB clock of 80 MHz. Using this clock it won't be possible to operate with the CANopen standard bit rates of 5kbit/s, 10kbit/s and 20kbit/s. Higher bit rates are no problem, all standard bitrates from 50kbit/s upwards work.

Is there a possibility to use a different and slower clock for the CAN controller?

[rudi ;-)]

Hi all,

The ESP32 CAN controller is clocked with APB clock of 80 MHz. Using this clock it won't be possible to operate with the CANopen standard bit rates of 5kbit/s, 10kbit/s and 20kbit/s. Higher bit rates are no problem, all standard bitrates from 50kbit/s upwards work.

Is there a possibility to use a different and slower clock for the CAN controller?

not sure i understand right ( english is not my mother language )
but i think you would use CAN with slower baud right?

slower as 50kbit/s does not work? really?

have you tried

Code: Select all

/** \brief CAN Node Bus speed */
typedef enum  {
	CAN_SPEED_1KBPS=1, 					/**< \brief CAN Node runs at 1kBit/s. */
	CAN_SPEED_5KBPS=5, 				  	/**< \brief CAN Node runs at 5kBit/s. */
	CAN_SPEED_10KBPS=10, 				/**< \brief CAN Node runs at 10kBit/s. */
	CAN_SPEED_12KBPS=12, 				/**< \brief CAN Node runs at 12kBit/s. */
	CAN_SPEED_15KBPS=15, 				/**< \brief CAN Node runs at 15kBit/s. */
	CAN_SPEED_20KBPS=20, 				/**< \brief CAN Node runs at 20kBit/s. */
	CAN_SPEED_25KBPS=25, 				/**< \brief CAN Node runs at 25Bit/s. */
	CAN_SPEED_50KBPS=50, 				/**< \brief CAN Node runs at 50kBit/s. */
	CAN_SPEED_100KBPS=100, 				/**< \brief CAN Node runs at 100kBit/s. */
	CAN_SPEED_125KBPS=125, 				/**< \brief CAN Node runs at 125kBit/s. */
	CAN_SPEED_250KBPS=250, 				/**< \brief CAN Node runs at 250kBit/s. */
	CAN_SPEED_500KBPS=500, 				/**< \brief CAN Node runs at 500kBit/s. */
	CAN_SPEED_800KBPS=800, 				/**< \brief CAN Node runs at 800kBit/s. */
	CAN_SPEED_1000KBPS=1000				/**< \brief CAN Node runs at 1000kBit/s. */
}CAN_speed_t;

you can edit all nice and pre set all nice if you want

hope this helps
best wishes
rudi

edit: as info for you from a cross link: UART theme

master clock is the APB clock which is 80MHz by default.
The integer portion of the clock divider register is 20 bits wide, which gives a theoretical minimum speed of 76bps
You would you need a 24 bit divider to divide 80MHz down to 5Hz.

[hwmaier]

@rudi: Its not a matter of software but hardware capabilities of the ESP32 chip.

The baud rate prescaler in the SJA1000 is only 6 bit wide, resulting in a max pre-scaler value of 64. As a result the longest time quanta achievable is 1.6us. The max number of time quanta we can use with a SJA1000 is 25, resulting in a longest bit length of 40us and a lowest bit rate of 25000 bps.

The CANopen standard defines baudrates of 5k, 10k, 20k, 50k, 125k, 250k, 500k, 800k and 1000k bps.

CANopen baudrates of 5k, 10k and 20k are impossible to configure unless the ESP32 allows the CAN bus to operate with a slower lock, like the RTC8M clock.

And this was my question, is there an option to use a slower clock than the 80MHz APB clock?

[hwmaier]

In order to achieve a 10kbps CAN bitrate, the clock speed for the CAN controller must not be higher than 32 MHz.

The CAN controller is not documented much, so I am hoping that there is a register to either pre-scale the clock or a clock divider of some sort or to use a different and slower clock source rather the APB_CLK.

[hwmaier]

This also can be verified using a CAN bit rate calculator like this one:

https://www.kvaser.com/support/calculat ... alculator/

[rudi ;-)]

The CAN driver we use in EPS32 basically is compatible with the SJA1000 CAN controller

what says the datasheet

bus0.jpg (72.22 KiB) Viewed 18999 times

BRP-0.jpg (45.12 KiB) Viewed 18999 times

what info we have about the CAN Register

...

[rudi ;-)]

so you want to know about CAN document and Timer Document right?

[hwmaier]

@rudi: Thank you for your replies.

I am aware that the CAN controller is a SJA1000 and I have worked with the SJA1000 before, so know the chip quite well. I also have access to the ESP32 Technical Reference. But the ESP32 offers little information about the possible clock sources of the CAN controller.

I do not want information about the CAN controller itself. The SJA1000 is well documented in its datasheet. I want information about the clock sources for the CAN controller.

2017-06-13_21-37-18.jpg (75.06 KiB) Viewed 18994 times

Most peripherals have multiple clock sources, so what about the CAN controller?

Can another (slower) clock than 80MHz be configured for the CAN controller?

[ESP_igrr]

I have checked with the hardware team, and there is no divider or clock mux which could be used to lower the input clock of CAN controller independently from the APB clock, unfortunately.

[hwmaier]

@ESP_igrr Thank you for the clarification. Your support is excellent.

However I must admit I was hoping there would be a solution.

The fact that the clock frequency for the CAN controller cannot be reduced does put some limits on the usage scenarios for the ESP32 CAN. Without being able to reduce the clock, it is not possible to set the baud rate prescaler to a suitable value for 10000 bps and 20000 bps baudrates. This means a hardware using the ESP32 CAN would never be able to achieve CANopen compliance as the 20000 bps for example is a mandatory bit rate for CANopen.

I didn't really expect this limit and this came a bit as a surprise.

Is there any way to reduce the APB clock frequency? I tried using the call rtc_clk_apb_freq_update and also to change the APB_CLK_FREQ macro. Both did not have any effect.