ESP32 Forum

Posted: **Wed May 22, 2019 4:41 pm**

Hello together,
perhaps you can help me with this:
I am trying to get I2S and Ethernet (over LAN8720) working at the same time, but I think this is not possible if MCLK and 50MHz Ethernet Clock via APLL is needed for both modules.

Am I right and does someone know a workaround to force the ethernet driver to not change my APLL that I need for the I2S Master Clock?
As far as I can see this code is called in esp_eth_init() to set 50MHz no matter what eth_clock_mode_t type I have selected.

Code: Select all

//emac_main.c
esp_err_t esp_eth_init_internal(eth_config_t *config)
{
....
      // 50 MHz = 40MHz * (6 + 4) / (2 * (2 + 2) = 400MHz / 8
        rtc_clk_apll_enable(1, 0, 0, 6, 2);
        REG_SET_FIELD(EMAC_EX_CLKOUT_CONF_REG, EMAC_EX_CLK_OUT_H_DIV_NUM, 0);
        REG_SET_FIELD(EMAC_EX_CLKOUT_CONF_REG, EMAC_EX_CLK_OUT_DIV_NUM, 0);
        
        if (emac_config.clock_mode == ETH_CLOCK_GPIO0_OUT) {
            PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_CLK_OUT1);
            REG_WRITE(PIN_CTRL, 6);
            ESP_LOGD(TAG, "EMAC 50MHz clock output on GPIO0");
        } else if (emac_config.clock_mode == ETH_CLOCK_GPIO16_OUT) {
            PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT);
            ESP_LOGD(TAG, "EMAC 50MHz clock output on GPIO16");
        } else if (emac_config.clock_mode == ETH_CLOCK_GPIO17_OUT) {
            PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO17_U, FUNC_GPIO17_EMAC_CLK_OUT_180);
            ESP_LOGD(TAG, "EMAC 50MHz inverted clock output on GPIO17");
        }
    }
....
}

Posted: **Thu May 23, 2019 4:29 am**

Correct, you would have to use external 50mhz clock with ETH_CLOCK_GPIO0_IN

If you are not using WiFi or BT you might be able to run the bbpll at a custom frequency and hack your way to 50mhz on clk_out but I am not sure this is possible.

Posted: **Thu May 23, 2019 8:09 am**

Alternatively, if you don't care about exact I2S frequencies, you can possibly also run that from the BPLL and free up the APLL for Ethernet.

Posted: **Thu May 23, 2019 8:15 am**

OK, thanks for your quick replies!

but assuming I have a 50MHz OSC and connected to IO0 (layout is not finisehd, so I can add the OSC):
I have to initialize the Ethernet driver first, because it always initializes the apll to 50MHz as far as I can see, no matter what flag eth_clock_mode_t is set.
If I afterwards initialize the I2S Module which also calculates an accurate I2S mclk frequency via the apll and it will output it on IO0 per default as far as I can see in the i2s driver.
I afterwards only have to change the GPIO Mapping for the mclk (apll clk out) to a different pin because IO0 is needed for the 50MHz OSC clk in.
What do you think, is this a possibility?

Posted: **Thu May 23, 2019 11:52 am**

Volvox wrote: ↑
Thu May 23, 2019 8:15 am
I have to initialize the Ethernet driver first, because it always initializes the apll to 50MHz as far as I can see, no matter what flag eth_clock_mode_t is set.

Code: Select all

    if (emac_config.clock_mode != ETH_CLOCK_GPIO0_IN) {
 ...
        rtc_clk_apll_enable(1, 0, 0, 6, 2);
 ...        
    }

Posted: **Mon May 27, 2019 5:33 pm**

Sorry, my mistake.. I have not seen the if{} at the beginning.

Concerning the purpose:
I have to get audio data from ethernet and need it to play via I2S. So the whole thing is mainly an audio solution, so a proper audio clock is required.

But to be save for the future the Wifi/Bt module will also be used later, so I am not sure if hacking the bbpll is the best solution here.

But my problem now is kind of a "How-to-setup-the-whole-thing-in-the-right-order" problem I think.

As far as I know:
Even if I use the external 50MHz crystal for ethernet, the input of this clock on GPIO0 is mandatory. (Or can I use this pin for I2S APLL now? I do not know exactly if this external 50MHz clock is needed by the ESP to send frames in-sync to the PHY IC)
But I now have the apll free for I2S.

Assuming it is mandatory: When now installing the I2S driver, the i2s module will default use GPIO0 or CLK_OUT1 for apll located also on GPIO0 as clockout as far as I can see which overwrites the Ethernet Clock Input on same GPIO0.

The apll alternative CLK_OUT2 and 3 are on RX and TX pins, so perhaps I can use the in my solution not used RX (while running the program)

Code: Select all

PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_CLK_OUT2); //pinmapping for apll
//A second unknown line here to let the I2S0 use the CLK_OUT2 for apll out?

So my question is how to set this whole thing (Ethernet MAC and I2S0) up in a proper sequence to get every clocks working.
Perhaps you can help me with my confusion.

Posted: **Tue Sep 03, 2019 5:59 am**

Only saw you post now, so my answer may not be relevant anymore but may help others in the future.

If you use Ethernet, GPIO0 is taken either as clock input or output and CLK_OUT1 cannot be used other than for 50MHz.

You are also limited in the clock frequencies you can configure for I2S if the APLL is used for Ethernet CLK_OUT.

You can output another lock on either CLK_OUT2 or CLK_OUT3. CLK_OUT2 is preferred as you do not loose debug output. If you put a 1k series resistor between GPIO3/U0RXD and the USB chip, you still can upload programs and use the clock while your application is running.

This snippet wires 50MHz APLL clock to GPIO0 for Ethernet and a 40MHz I2S clock using the PLL_D2_CLK to GPIO3:

Code: Select all

    
    // Enable the I2S peripheral
    periph_module_enable(PERIPH_I2S0_MODULE);
    
    // Configure Audio PLL to 50 MHz.
    rtc_clk_apll_enable(true, 0 /*sdm0*/, 0 /*sdm1*/, 6 /*sdm2*/, 2 /*odiv*/); // 50 MHz

    // Set I2S0_CLk to 40 MHz
    WRITE_PERI_REG(I2S_CLKM_CONF_REG(0),  // Set I2S0 clock
                  I2S_CLK_EN | // Use PLL_D2_CLK which is 160MHz
                  (0 << I2S_CLKM_DIV_A_S) |
                  (0 << I2S_CLKM_DIV_B_S) |
                  (4 << I2S_CLKM_DIV_NUM_S)); // Divide by 4 to generate 40 MHz from PLL_D2_CLK
    
    // This is undocumented but outputs 50MHz on GPIO0_CLK_OUT1 and I2S0_CLK on CLK_OUT2
    WRITE_PERI_REG(PIN_CTRL, (6 << CLK_OUT1_S) | (0x0 << CLK_OUT2_S) | (0xF << CLK_OUT3_S));
    // Output CLK_OUT1 on GPIO0
    PIN_FUNC_SELECT(GPIO_PIN_REG_0, FUNC_GPIO0_CLK_OUT1);
    // Output CLK_OUT1 on GPIO3 (U0RXD),
    // hardware needs a 1k serial resistor here to avoid USB UART driving...
    PIN_FUNC_SELECT(GPIO_PIN_REG_3, FUNC_U0RXD_CLK_OUT2);

Posted: **Wed Oct 23, 2019 8:15 pm**

I am running into the same issue now. What was the pinout you have for the Ethernet and i2S ? I am trying to hookup a LAN8710 and max98367a together.

Thanks

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