ESP32-PICO-D4 boot loop

[dimoesp]

I have a custom board with the ESP32-PICO-D4 , I can program it but it gets stuck into a boot loop.
I tried changing all the modes and changing the SPI bus speed. Still the same issue.
The board is based on the PICO-D4 reference design. I have left out the pull-up on IO12 to enable 3V3 operation.

I also dumped the fuses and I see that the SPI pins are already set.
I tried programming with both the Arduino IDE and the IDF and still the same issue.

Any suggestions would be appreciated.
I tried searching on the forum for any solutions but I don't see any fix.

Code: Select all

esptool.py v2.3.1
Flashing binaries to serial port COM16 (app at offset 0x10000)...
esptool.py v2.3.1
Connecting.....
Chip is ESP32-PICO-D4 (revision 0)
Features: WiFi, BT, Dual Core, Embedded Flash
Uploading stub...
Running stub...
Stub running...
Configuring flash size...
Auto-detected Flash size: 4MB
Flash params set to 0x0320
Compressed 23696 bytes to 13355...
Wrote 23696 bytes (13355 compressed) at 0x00001000 in 1.2 seconds (effective 161.8 kbit/s)...
Hash of data verified.
Compressed 457792 bytes to 303931...
Wrote 457792 bytes (303931 compressed) at 0x00010000 in 26.8 seconds (effective 136.7 kbit/s)...
Hash of data verified.
Compressed 3072 bytes to 103...
Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 786.6 kbit/s)...
Hash of data verified.

Leaving...
Hard resetting via RTS pin...
MONITOR
--- idf_monitor on COM16 115200 ---
--- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H ---
ets Jun  8 2016 00:22:57

rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DOUT, clock div:2
load:0x3fff0018,len:4
load:0x3fff001c,len:7916
load:0x40078000,len:0
load:0x40078000,len:15684
entry 0x400786dc
ets Jun  8 2016 00:22:57

rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DOUT, clock div:2
load:0x3fff0018,len:4
load:0x3fff001c,len:7916
load:0x40078000,len:0
load:0x40078000,len:15684
entry 0x400786dc
ets Jun  8 2016 00:22:57

rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DOUT, clock div:2
load:0x3fff0018,len:4
load:0x3fff001c,len:7916
load:0x40078000,len:0
load:0x40078000,len:15684
entry 0x400786dc

Code: Select all

espefuse.py v2.4.1-dev
Connecting....
Efuse fuses:
WR_DIS                 Efuse write disable mask                          = 0 R/W (0x0)
RD_DIS                 Efuse read disablemask                            = 0 R/W (0x0)
CODING_SCHEME          Efuse variable block length scheme                = 0 R/W (0x0)
KEY_STATUS             Usage of efuse block 3 (reserved)                 = 0 R/W (0x0)

Security fuses:
FLASH_CRYPT_CNT        Flash encryption mode counter                     = 0 R/W (0x0)
FLASH_CRYPT_CONFIG     Flash encryption config (key tweak bits)          = 0 R/W (0x0)
CONSOLE_DEBUG_DISABLE  Disable ROM BASIC interpreter fallback            = 1 R/W (0x1)
ABS_DONE_0             secure boot enabled for bootloader                = 0 R/W (0x0)
ABS_DONE_1             secure boot abstract 1 locked                     = 0 R/W (0x0)
JTAG_DISABLE           Disable JTAG                                      = 0 R/W (0x0)
DISABLE_DL_ENCRYPT     Disable flash encryption in UART bootloader       = 0 R/W (0x0)
DISABLE_DL_DECRYPT     Disable flash decryption in UART bootloader       = 0 R/W (0x0)
DISABLE_DL_CACHE       Disable flash cache in UART bootloader            = 0 R/W (0x0)
BLK1                   Flash encryption key
  = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLK2                   Secure boot key
  = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLK3                   Variable Block 3
  = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W

Config fuses:
XPD_SDIO_FORCE         Ignore MTDI pin (GPIO12) for VDD_SDIO on reset    = 0 R/W (0x0)
XPD_SDIO_REG           If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset   = 0 R/W (0x0)
XPD_SDIO_TIEH          If XPD_SDIO_FORCE & XPD_SDIO_REG, 1=3.3V 0=1.8V   = 0 R/W (0x0)
SPI_PAD_CONFIG_CLK     Override SD_CLK pad (GPIO6/SPICLK)                = 6 R/W (0x6)
SPI_PAD_CONFIG_Q       Override SD_DATA_0 pad (GPIO7/SPIQ)               = 17 R/W (0x11)
SPI_PAD_CONFIG_D       Override SD_DATA_1 pad (GPIO8/SPID)               = 8 R/W (0x8)
SPI_PAD_CONFIG_HD      Override SD_DATA_2 pad (GPIO9/SPIHD)              = 11 R/W (0xb)
SPI_PAD_CONFIG_CS0     Override SD_CMD pad (GPIO11/SPICS0)               = 16 R/W (0x10)
DISABLE_SDIO_HOST      Disable SDIO host                                 = 0 R/W (0x0)

Calibration fuses:
BLK3_PART_RESERVE      BLOCK3 partially served for ADC calibration data  = 0 R/W (0x0)
ADC_VREF               Voltage reference calibration                     = 1100 R/W (0x0)

Identity fuses:
MAC                    MAC Address
  = d8:a0:1d:40:e0:44 (CRC 90 OK) R/W
CHIP_VER_REV1          Silicon Revision 1                                = 0 R/W (0x0)
CHIP_VERSION           Reserved for future chip versions                 = 0 R/W (0x0)
CHIP_PACKAGE           Chip package identifier                           = 5 R/W (0x5)

Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V).

--demi

[ESP_igrr]

Could you please set bootloader log level to "Verbose" and give it a try? It looks like SPI flash is okay and 2nd stage bootloader gets loaded, but crashes for some reason. Maybe log output will have some extra info.

[dimoesp]

It's already set to verbose but nothing gets printed so I'm just wondering how can this be.
The only thing that is different from other ESP chipsets is that SPIWP is set to 0xee. and configsip is not 0x00.

BootloaderVerbose.png (4.69 KiB) Viewed 15434 times

issue.png (59.36 KiB) Viewed 15434 times

[deandob]

Hi,

I have the same problem - how did you resolve this?

[hassan789]

looks like a power issue... do you ensure that the enable pin powered up after the analog power?
Can you share your schematic?

[deandob]

Yes, there is a delay (10K & 0.1uF) on the EN line from VCC.
Oscilloscope screenshots, schematic and layout can be found in this PDF: https://1drv.ms/b/s!ApUB68SilQqFhuMzLHlyS3dn1-D2HA
Based on the other thread I opened over the weekend https://www.esp32.com/viewtopic.php?f=1 ... 6&start=10, I think (but not 100% sure) the issue is my board layout, as the power is stable and I can bypass the onboard SMPS with an external power supply powering other working ESP32 boards with the same result.

If you see anything unusual not already called out, do let me know. I'm in the process of redesigning the PCB to allow for more unbroken ground plane.

[ESP_igrr]

One extra thing I may suggest is to order a known-to-work board with PICO chip on it, and then transplant one of your chips onto that board. This way you rule out the possibility that the chips you have received have some issue.

[deandob]

Good idea, will try that

[hassan789]

Your reset signal should be before the resistor... why did you place them after?

[deandob]

I don't understand - if the reset signal is before the resistor then it will be constantly tied to Vcc.

The schematic as drawn will have EN/RESET high except for the RC constant during power up, and when the reset button is pressed, will go low to reset the MCU. This is consistent with the PICO D4 data sheet, unless you mean R4 which is after the switch, but this is populated as 0R so I have omitted it from my design.