What does third NPN Line on ESP32[xy] UART Auto Program reference circuits do?

[espmpo]

Hi,
We are working on our own prototype production boards utilizing the reference design for the auto program switch that can be found in ESP designs like the "Switch" section of https://dl.espressif.com/dl/schematics/ ... T_V4_1.pdf.
The truth table and timing sequence for auto program shows the relationship between the input DTR and RTS UART lines and the output to the ESP32[xy] chip lines EN and IO0. In some other message boards' discussion with (earlier) reference designs those two are the only lines in. However, in Espressif's own designs there is a third line in via the NPN circuits.

In the ESP32's case it is IO2, in the ESP32S3's case it is IO46.

Being a coder and only a neophyte EE what purpose does this third line serve? It is helping with getting the chip in a mode to receive a flash upload?
What would things look like if the Auto Program truth table was extend with another column for this third line?

Thanks for any insight,
mpo

[MicroController]

in Espressif's own designs there is a third line

Where?
Can't find one on the DevKit for example.