Thanks for the response, WiFive! I found (in the SDK headers) I2C_DATA_APB_REG having an offset of 0x1C to the I2C module base address (0x3FF5.3000 or 0x3FF6.7000) , while RTC_I2C_DATA_REG has an offset of 0x1C to the DR_REG_RTC_I2C_BASE (0x3ff48C00), which seems to be the third I2C module located i...

Hi, I am trying to understand the I2C data buffer concept. According to the Technical Reference Manual v.3.4, chapter 11, page 278, there is a 32 words buffer at REG_I2C_BASE + 0x100. Each byte received or transmitted is stored in the lower 8 bits of a buffer word, the upper 24 bits are unused. Then...

Hi folks, The I2C_END_DETECT_INT_RAW interrupt request source bit is mentioned in chapter 11.3.7 of the ESP32 Technical Reference Manual v.3.4, but does not appear in the I2C_INT_RAW_REG register description in chapter 11.5. According to the SDK esp32/include/soc/i2c_reg.h line 331 and strangely mis...

Thanks!
I haven't looked into the SDK yet, but I thing that is certainly a good idea...

Hi folks, in the ESP32 Technical Reference Manual p.36, chapter 2.3.2 CPU Interrupt, table 9, is a list of CPU interrupts and their priority level numbers, but I can't find a statement about their precedence. Is level 0 the highest (after NMI), or level 5? And: Can a higher priority interrupt reques...