The synchronization between the cores is definitely related to NVS access. I saw that when the ESP performs a core dump, it can write to NVS *without* syncing with the second core. In another thread I asked the question if I could use the same trick: https://esp32.com/viewtopic.php?f=2&t=10901 Someo...

Forgot to mention that on core 1 I do not call any ESP-related API; only memory-mapped I/O on some GPIO pins. So I know that core 1 is not doing anything with SPI.

If I wanted to continue to use NVS API on core 0, would it be OK to call after turning off interrupts on core 1?

Hi. I want to use core 1 to poll GPIO pins in a tight loop. In order for fastest response, I am turning off interrupts on core 1 (read this post for a rationale for doing this: https://esp32.com/viewtopic.php?f=2&t=10006). Turning off interrupts on core 1 via portDISABLE_INTERRUPTS() and disabling t...

more digging: the problem seems to be indeed related to IPC. I logged esp_ipc_call() for core 1 and I was surprised how much code is executed on that core. E.g., calling nvs_flash_init() will trigger esp_ipc_call() on core 1. If interrupts are disabled on core 1 at that moment, then the ESP32 will j...

followup to my own question. portDISABLE_INTERRUPTS() only disables interrupts on the core where that function is called. So in the scenario discussed here, interrupts on core 0 are still enabled. However, I have noticed that FreeRTOS will create an "ipc" task on core 1. I wonder if disabling interr...

Thanks for the nice explanations. I have been trying the same thing. I have a question about portDISABLE_INTERRUPTS(): does this turn off interrupts only on the core where that function is called or turn off interrupts for both cores? I am calling this function on core 1, but then I noticed some unu...

thx! Exactly what I've been looking for!

I am using an ESP to serve the I/O bus of an old 8-bit CPU (a Z80). The ROM running on the Z80 sometimes runs a tight loop where it constantly polls the I/O bus. I want to make serving the Z80's I/O bus as deterministic as possible by dedicating one core to that task. That core will constantly poll ...

Hi,
is there a way to disable all interrupts on a core? I was looking for an assembly instruction that would do that but cannot find one.
TIA,
AP